dear experts,
I have a custom board with TDA4. SDK is 8.2. 4 ethernet devices connected at SGMII1..3 as in table below
| MAC port | SERDES port | SERDES lane | peripheral | ETH PHY | type |
| ENET1 | SERDES0 | lane0 | SGMII1 | RTL9010 | PHY |
| ENET2 | SERDES0 | lane1 | SGMII2 | 88Q3344 | PHY |
| ENET3 | SERDES1 | lane0 | SGMII3 | RTL9086 | MAC2MAC |
| ENET4 | SERDES1 | lane1 | SGMII4 | RTL9010 | PHY |
The MCU2_0 firmware gets caught in an infinite loop in CSL_serdesLaneEnable() while waiting for PLL lock at the first I/F SERDES0_0.
Call sequence is EnetBoard_setPhyConfig() -> EnetBoard_setPhyConfigSgmii() -> Board_serdesCfgSgmii() -> Board_CfgSgmii() -> CSL_serdesLaneEnable().
All through the reset sequence of the function CSL_serdesLaneEnable() the register PLLLNC_STATUS_PREG__PLLCTRL_STATUS_PREG_j (@ 0x05004088) is eq. 0x00000000. The description in spruil1c/J721E_registers4 is quite slim. What can be the reason(s) for the PLL not to lock?
Is there any documentation, application note available on how to set up SGMII?
Pls. support
best Stefan
