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Omap L138, DSP-Part, McBsp with EDMA3

Volker Rumm
Prodigy 80 points
Other Parts Discussed in Thread: OMAP-L138

Hello, I develop on Omap L138, DSP-Part a McBsp with EDMA3. I am using CCS 4.2.3.00004.

The external device is the master and the Dsp is the slave.

The McBsp is running well, because receiving by polling is good.

So now I want to move the incomming data into internal buffer (buffer1 and buffer2 are switching) using EDMA3.

In memory watch and register watch I don't see changing anything what the programm is doing.

All registers are always 0.

Here is my program :

    in_buffer1 = (int*) EDMA3_INBUFFER1;
    in_buffer1_last = (int*) EDMA3_INBUFFER1_LAST;
    in_buffer2 = (int*) EDMA3_INBUFFER2;
    in_buffer2_last = (int*) EDMA3_INBUFFER2_LAST;

    CSL_FINS(edma3cc0Regs->EESR,                     EDMA3CC_EVENT_ETYPE,          3); // enable event on 1st channel
    CSL_FINS(edma3cc0Regs->ESR,                      EDMA3CC_EVENT_ETYPE,          3); // clear pending event on 1st channel
   
    CSL_FINST(edma3cc0Regs->PARAMSET[0].OPT,         EDMA3CC_OPT_ITCINTEN,         ENABLE);  // int enable
    CSL_FINS(edma3cc0Regs->PARAMSET[0].OPT,          EDMA3CC_OPT_TCC,              1); 
    CSL_FINS(edma3cc0Regs->PARAMSET[0].SRC,          EDMA3CC_SRC_SRC,              CSL_MCBSP_1_CTRL_REGS);  // McBsp1 is source
    CSL_FINS(edma3cc0Regs->PARAMSET[0].A_B_CNT,      EDMA3CC_A_B_CNT_ACNT,         1);
    CSL_FINS(edma3cc0Regs->PARAMSET[0].A_B_CNT,      EDMA3CC_A_B_CNT_BCNT,         EDMA3_BUFFER_SIZE);
    CSL_FINS(edma3cc0Regs->PARAMSET[0].DST,          EDMA3CC_DST_DST,              (Uint32)in_buffer1);  //in_buffer1 is destination
    CSL_FINS(edma3cc0Regs->PARAMSET[0].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 1);
    CSL_FINS(edma3cc0Regs->PARAMSET[0].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0);
    CSL_FINS(edma3cc0Regs->PARAMSET[0].LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_BCNTRLD, (Uint16)&edma3cc0Regs->PARAMSET[1]); // next param set [1]
    CSL_FINS(edma3cc0Regs->PARAMSET[0].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0);
    CSL_FINS(edma3cc0Regs->PARAMSET[0].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0);
    CSL_FINS(edma3cc0Regs->PARAMSET[0].CCNT,         EDMA3CC_CCNT_CCNT,            1);
     
    CSL_FINST(edma3cc0Regs->PARAMSET[1].OPT,         EDMA3CC_OPT_ITCINTEN,         ENABLE);  // int enable
    CSL_FINS(edma3cc0Regs->PARAMSET[1].OPT,          EDMA3CC_OPT_TCC,              2); 
    CSL_FINS(edma3cc0Regs->PARAMSET[1].SRC,          EDMA3CC_SRC_SRC,              CSL_MCBSP_1_CTRL_REGS);  // McBsp1 is source
    CSL_FINS(edma3cc0Regs->PARAMSET[1].A_B_CNT,      EDMA3CC_A_B_CNT_ACNT,         1);
    CSL_FINS(edma3cc0Regs->PARAMSET[1].A_B_CNT,      EDMA3CC_A_B_CNT_BCNT,         EDMA3_BUFFER_SIZE);
    CSL_FINS(edma3cc0Regs->PARAMSET[1].DST,          EDMA3CC_DST_DST,              (Uint32)in_buffer2);  //in_buffer2 is destination
    CSL_FINS(edma3cc0Regs->PARAMSET[1].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 1);
    CSL_FINS(edma3cc0Regs->PARAMSET[1].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0);
    CSL_FINS(edma3cc0Regs->PARAMSET[1].LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_BCNTRLD, (Uint16)&edma3cc0Regs->PARAMSET[2]); // next param set [0]
    CSL_FINS(edma3cc0Regs->PARAMSET[1].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0);
    CSL_FINS(edma3cc0Regs->PARAMSET[1].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0);
    CSL_FINS(edma3cc0Regs->PARAMSET[1].CCNT,         EDMA3CC_CCNT_CCNT,            1);
     
    CSL_FINST(edma3cc0Regs->PARAMSET[2].OPT,         EDMA3CC_OPT_ITCINTEN,         ENABLE);  // int enable
    CSL_FINS(edma3cc0Regs->PARAMSET[2].OPT,          EDMA3CC_OPT_TCC,              1); 
    CSL_FINS(edma3cc0Regs->PARAMSET[2].SRC,          EDMA3CC_SRC_SRC,              CSL_MCBSP_1_CTRL_REGS);  // McBsp1 is source
    CSL_FINS(edma3cc0Regs->PARAMSET[2].A_B_CNT,      EDMA3CC_A_B_CNT_ACNT,         1);
    CSL_FINS(edma3cc0Regs->PARAMSET[2].A_B_CNT,      EDMA3CC_A_B_CNT_BCNT,         EDMA3_BUFFER_SIZE);
    CSL_FINS(edma3cc0Regs->PARAMSET[2].DST,          EDMA3CC_DST_DST,              (Uint16)in_buffer1);  //in_buffer1 is destination
    CSL_FINS(edma3cc0Regs->PARAMSET[2].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_DSTBIDX, 1);
    CSL_FINS(edma3cc0Regs->PARAMSET[2].SRC_DST_BIDX, EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0);
    CSL_FINS(edma3cc0Regs->PARAMSET[2].LINK_BCNTRLD, EDMA3CC_LINK_BCNTRLD_BCNTRLD, (Uint32)&edma3cc0Regs->PARAMSET[1]); // next param set [1]
    CSL_FINS(edma3cc0Regs->PARAMSET[2].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0);
    CSL_FINS(edma3cc0Regs->PARAMSET[2].SRC_DST_CIDX, EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0);
    CSL_FINS(edma3cc0Regs->PARAMSET[2].CCNT,         EDMA3CC_CCNT_CCNT,            1);
     
    // Enable EDMA3 Interrupts
    edma3cc0Regs->IER = 1;
    CSL_FINST(edma3cc0Regs->IER, EDMA3CC_IER_I0, ENABLE);
   
    // Map EDMA system interrupts to DSP INT5
    CSL_FINS(dspintcRegs->INTMUX1, DSPINTC_INTMUX1_INTSEL5,    CSL_INTC_EVENTID_EDMA3_0_CC0_INT1);
}

The interrupt 5 in IER is enabled on another place.

What is the reason for this ?

May I use IDMA ?

Volker

  • 0
    TI__Genius 14545 points

    Volker,

       In my experience, typically when all the registers of a particular peripheral remain at zero, it means that the peripheral is powered down on the chip. Can you check the to see if the EDMA3 is powered up?

  • 0 in reply to dabuan
    Prodigy 80 points

    Hello Drew,

    Thank you, the EDMA was eally powered down.

    Now I can't see the edma3cc0Regs->PARAMSET-Array in the register view. An  additional problem is, that all EDMA-registers are not named in the view.

    But a much bigger problem is, that the EDMA3 is not copying the data.

    Do you have a sample in source-code (reading mcbsp and put the data into ping pong buffer) ?

     

    Volker

     

  • 0 in reply to Volker Rumm
    TI__Genius 14545 points

    Volker,

      There should be a ping pong buffer example in this package  I don't think it reads from McBSP, but it should be enough to get you started with configuring the EDMA3 registers to complete a transaction.

  • 0 in reply to dabuan
    Prodigy 80 points

    Hello Drew,

     

    thank you for the link. I picked the ping pong example and expanded it to continously one.

    Now I must read the data from mcbsp1 and not from memory. I don't know, how to do it.

    In the document sprugp9b I found the hint, that the CONST mode is not suppurted on L1x-processors.

    Here is my example code :

    static void init_PaRAM_event10 (void)
    {
        // Reset EDMA PaRAM OPT Register
        edma3cc0Regs->PARAMSET[EDMA_EVENT10].OPT = CSL_EDMA3CC_OPT_RESETVAL;
       
        // Config PaRAM OPT (Enable TC & ITC Chaining; Set TCC)
        edma3cc0Regs->PARAMSET[EDMA_EVENT10].OPT =
            CSL_FMKT(EDMA3CC_OPT_ITCCHEN, ENABLE) |
            CSL_FMKT(EDMA3CC_OPT_TCCHEN, ENABLE) |
            CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
            CSL_FMKT(EDMA3CC_OPT_ITCINTEN, ENABLE) |
            CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT11);
       
        // Initialize EDMA Event Src and Dst Addresses
        edma3cc0Regs->PARAMSET[EDMA_EVENT10].SRC = (Uint32)&srcBuffer1[0]; //CSL_MCBSP_1_CTRL_REGS;
        edma3cc0Regs->PARAMSET[EDMA_EVENT10].DST = (Uint32)in_buffer1;
       
        // Set EDMA Event PaRAM A,B,C CNT
        edma3cc0Regs->PARAMSET[EDMA_EVENT10].A_B_CNT =
            CSL_FMK(EDMA3CC_A_B_CNT_ACNT, EDMA3_BUFFER_SIZE) |
            CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 1);
        edma3cc0Regs->PARAMSET[EDMA_EVENT10].CCNT = 1;
       
        // Set EDMA Event PaRAM SRC/DST BIDX
        edma3cc0Regs->PARAMSET[EDMA_EVENT10].SRC_DST_BIDX =
            CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, EDMA3_BUFFER_SIZE) |
            CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, EDMA3_BUFFER_SIZE);
       
        // Set EDMA Event PaRAM SRC/DST CIDX
        edma3cc0Regs->PARAMSET[EDMA_EVENT10].SRC_DST_CIDX =
            CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) |
            CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0);
       
        // Set EDMA Event PaRAM LINK and BCNTRLD
        edma3cc0Regs->PARAMSET[EDMA_EVENT10].LINK_BCNTRLD =
            CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint16)&edma3cc0Regs->PARAMSET[EDMA_EVENT11]) |
            CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 0);
    }/* init_PaRAM_event10 */

    The functions init_PaRAM_event11() and init_PaRAM_event12() are very similar.

    Please tell me what I have to do.

    Volker

     

  • 0 in reply to Volker Rumm
    TI__Genius 14545 points

    Volker Rumm said:
    Now I must read the data from mcbsp1 and not from memory. I don't know, how to do it.

     

    You'll need to configure the EDMA3 Parameter Set to suite the source address of the McBSP register to read from. Example of this setup can be found in the EDMA3 User's Guide.

    The address of the McASP regsiters are found in the OMAP-L138 Datasheet. You'll need to use the Memory Map to determine exactly what address to read.

  • 0 in reply to Volker Rumm
    TI__Genius 14545 points

    Volker Rumm said:
    Now I must read the data from mcbsp1 and not from memory. I don't know, how to do it.

     

    You'll need to configure the EDMA3 Parameter Set to suite the source address of the McBSP register to read from. Example of this setup can be found in the EDMA3 User's Guide.

    The address of the McASP registers are found in the OMAP-L138 Datasheet. You'll need to use the Memory Map to determine exactly what address to read.