Hi,
I can understand when the DMA controller has to change between channels,
I, also, know the causes that makes the DMA switch between channels.
But, I can't understand how the DMA do that for one specific case.
When the DMA is reading data from a synchronized device and the RSYNC bit is set, the DMA has to wait for the synchronization signal, and while doing that, it has to change to other channels and do others transfers. That is exactly the problem, how the DMA changes to other transfers, since it has already send an address to the bus, and after the synchronization signal comes, it changes back to the first transfer that is synchronized, since the bus is already making another transfer?
Can the bus make two transfers at the same time? or the bus has some kind of logic control to switch between transfers?
I can't understand how the bus will act in this case...
Have I made my doubt clear?