• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 98 subscribers
  • Views 460 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Clock arrangement for C6678

haopeng han
Expert 1120 points
Other Parts Discussed in Thread: CDCLVD1204

Hi

For design simplicity, is it OK to use the following clock arrangement for C6678?

DDRCLK: 100MHz;  

CORECLK:  100MHz;  

PASSCLK:  100MHZ or CORECLK;   

SRIOSGMIICLK:  156.25MHz;    

MCMCLK:  156.25MHz;  

PCIECLK: 100MHZ.

The target frequencies of the DSP are CORE @1GHz; DDR3 @800MHz; SRIO @5GHz; PCIe @5GHz; Hyperlink @12.5GHz. 

I am gonna to use two LVDS oscillators (RMS Jitter = 1ps @12k~20MHz) one for 100MHz , one for 156.25MHz, and two clock buffers CDCLVD1204 for the clock fan-out. 

If it is OK, what I need to be aware of for the DSP functioning well?  Thanks.

Han

  • 0
    TI__Mastermind 42545 points

    These frequencies should be acceptable.  Are you connecting you're PCIE interface to some kind of backplane and, if yes, are you getting the PCIECLK from the backplane?  If not you may want to consider using the 156.25MHz clock for PCIE as well.  The higher reference clock frequencies are less susceptibleto Jitter.  If you are using a backplane clock for the PCIECLK be sure that it is electrically compatible.  PCIE backplane clocks are usually HCSL and a buffer would be needed for compatibility with the clock input.

  • 0 in reply to Bill Taboada
    Expert 1120 points

    Thank you for the information.