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TDA4VM: DMA transfer completion interrupt does not occur.

Erika Arakawa
Prodigy 10 points
Part Number: TDA4VM
Hi E2E team,

DMA transfers are not working as expected.
The UART driver we implemented calls the TI-PDK DMA driver.
Please answer the following questions.
(1)
The second DMA completion interrupt does not occur under the following conditions.
 * PDMA initialization parameters : elemCnt=4, fifoCnt=1
 * UART receive data size ： 16byte
It seems DMA has finished correctly, as the data is written to the destination address of the memory. ( see Sequence No.15 and 16)
Does anyone have an idea what the possible causes are?
Interrupt is set to Enable.
(2)
A DMA completion interrupt does not occur under the following conditions. (see Sequence No.9 )
 * PDMA initialization parameters : elemCnt=64, fifoCnt=64
 * UART receive data size : 16byte
Since the transfer size is not constant, I want to set elemCnt and fifoCnt as large as possible (i.e. UART FIFO size), and use the UART FIFO threshold exceeded interrupt to trigger DMA to transfer the data in the UART FIFO.
Is there any constraint on elemCnt and fifoCnt?
The calculation method of elemCnt and fifoCnt is as follows.
UART FIFO size is 64 bytes.
elemSize = UDMA_PDMA_ES_8BITS (= 0)
elemCnt = FIFO size / elemSize = 64byte / 8bit (= 1byte) = 64 (Size to read when PDMA receives a request)
fifoCnt = FIFO size / elemSize = 64byte / 8bit (= 1byte) = 64 (PDMA FIFO count)


Regards,

Erika Arakawa



  • 0
    TI__Guru**** 477995 points

    Hi ,

    Erika Arakawa said:
    (1)
    The second DMA completion interrupt does not occur under the following conditions.
     * PDMA initialization parameters : elemCnt=4, fifoCnt=1
     * UART receive data size ： 16byte
    It seems DMA has finished correctly, as the data is written to the destination address of the memory. ( see Sequence No.15 and 16)
    Does anyone have an idea what the possible causes are?
    Interrupt is set to Enable.

    Can you please try setting elemCnt and fifoCnt in the DMA registers? I see in the driver, that it is set everytime, transfer API is called. So can you please try setting it again?

    Erika Arakawa said:
    Is there any constraint on elemCnt and fifoCnt?

    Please set elemCnt and fifoCnt everytime you want to received data. Please refer to API UART_receiveDMA for these parameter's calculation..

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 10 points
    Hi Brijesh,

    Thank you for your reply.
    I'm trying to set elemCnt and fifoCnt everytime.
    By the way, could you give me the answer for 2 later?

    Regards,

    Erika Arakawa

  • 0 in reply to Erika Arakawa
    TI__Guru**** 477995 points

    Hi ,

    PDMA parameters should be set with the expected input size and should also match with the uart configuration. It shouldn't be set with the maximum possible expected size..

    Regards,

    Brijesh 

  • 0 in reply to Brijesh Jadav
    Prodigy 10 points

    Hi Brijesh,

    Sorry for the late reply.
    Thanks to your advice, the issue with receiving processing has been resolved.


    We also have questions about the sending process.

    We found a phenomenon that only 60 bytes are output when sending 64 bytes of data with the UART set to DMA mode 1 and the threshold set to 60 bytes. (Only 60 bytes have reached the terminal software of the other PC.)
    Note that when the descriptors were checked after the DMA transfer was completed, the transferred size was 64 bytes.
    The threshold is 60 bytes, but we expect 64 bytes to be sent.

    Each register setting considered necessary for DMA transfer is set as follows.

    DMA mode setting:
    - UART_SCR[0] DMA_MODE_CTL = 0
    - UART_FCR[3] DMA_MODE = 1

    FIFO threshold setting:
    - UART_SCR[6] TX_TRIG_GRANU1 = 0
    - UART_TLR[3-0] TX_FIFO_TRIG_DMA = 0xF

    Each DMA setting uses TI-PDK's UDMA driver, and the following settings are made with reference to TI-PDK's UART driver.

    ```

    int32_t ret;
    uint32_t xfer_size = 64U; /* Size of DMA transfer to be performed */
    uint32_t fifo_threshold = 60U; /* TX FIFO threshold */
    Udma_ChPdmaPrms param;

    UdmaChPdmaPrms_init(&param);

    if (xfer_size > fifo_threshold)

    {

        param.elemCnt = fifo_threshold;

    }

    else

    {

        param.elemCnt = xfer_size;

    }

    param.elemSize = UDMA_PDMA_ES_8BITS;

    param.fifoCnt = 0U;

    ret = Udma_chConfigPdma(p_ch_obj, &param);

    ```

    Are there any mistakes in the above settings?

    Or is there something missing in the settings?

  • 0 in reply to Erika Arakawa
    TI__Guru**** 477995 points

    Hi Erika,

    I think the transfer size should be multiple of fifo trigger level, isn't it? In this case, can you please try setting fifo trigger level to 4 bytes or even smaller 2 bytes? It would then transfer complete 64bytes.. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 10 points
    Currently, the receive process is working properly, but the transmit process is not working properly.
    As you responded, I am aware that the element count must be set to a multiple of the FIFO trigger level when receiving.
    Looking at the PDK code below, I don't think it is necessary to set the element count to a multiple of the FIFO trigger level when transmitting, is that correct?
    Or do I need to set the element count to a multiple of the FIFO trigger level even during transmission?
    drv/uart/soc/dma/v2/UART_dma.c::UART_transmitDMA()

        UdmaChPdmaPrms_init(&pdmaPrms);
    pdmaPrms.elemSize = 0; /* 8-bit */
    if ((uint32_t)size > (uint32_t)(hwAttrs->txTrigLvl))
    {
        pdmaPrms.elemCnt = (uint32_t)(hwAttrs->txTrigLvl);
    }
    else
    {
        pdmaPrms.elemCnt = (uint32_t)size;
    }
    pdmaPrms.fifoCnt = 0U;   /* Don't care for write */
    retVal = Udma_chConfigPdma(chHandle, &pdmaPrms);
  • 0 in reply to Erika Arakawa
    TI__Guru**** 477995 points

    Hi ,

    Not the element count in this API, but the total transfer size must be multiple of txTrigLvl. Can you please try setting txTrigLvl to be 2 or 4 and see if entire 64byts are correctly getting transferred ?

    Regards,

    Brijesh