Just a question to PCIe clock termination (50 ohm to GND). Datasheet says (chapter 9.3.3):
9.3.3 SERDES REFCLK Design Guidelines
The following section details the routing guidelines that must be observed when terminating the SERDES
REFCLK and is applicable only when SERDES REFCLK is configured to input mode.
- 50 Ω to GND is recommended on each leg.
- Internal AC coupling is always enabled, so external biasing is not needed.
https://www.ti.com/lit/ds/symlink/tda4vm.pdf
But design guide says (chapter 2.3.1):
PCIe clock shown in output clock mode. Termination resistors are to be removed for input clock mode.
https://www.ti.com/lit/an/spracp4/spracp4.pdf
Also it seems EVM uses the clocks as inputs and termination resistors are not populated. So I think design guide is correct but can you please check it and confirm?
Thanks
