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DRA829V: LPDDR4 config for custom board with XJ721E5BALF

Saravanakumar Balasubramanian
Prodigy 190 points
Part Number: DRA829V
Other Parts Discussed in Thread: DRA829

Hi Team,

We are using XJ721E5BALF processor and IS46LQ32256EA-062B2LA3 LPDDR4 memory in our custom board. Initially we were facing hang issue in first stage of bootloader in both eMMC and xSPI boot modes. We were using the DDR config dtsi file which was generated using the v0.6.0 of the DDR register configuration tool by TI.

After the suggestion from TI, they have updated the tool version to v0.9.1. Also they mentioned few changes impacting DRA829 which was listed below

Additionally, during the review of the DTSI file, have the following IO settings:

  • CA Drive Strength: 48 Ohm
  • CS Drive Strength: 34 Ohm
  • CA/CS ODT: 80 Ohm

 

As each channel has it’s own CS signal, but shared CA bus, they might consider using a CS drive strength of 60 or 80 ohm to be closer matched to the ODT value.

 

Changes between v0.6.0 and v0.9.1 impacting DRA829:

 

Updated write DQ training pattern (from 0x7 to 0x6) to prevent invalid training results observed in some systems
    - Register Updates
        > DDRSS_PHY_33, PHY_WDQLVL_PATT_0
        > DDRSS_PHY_289, PHY_WDQLVL_PATT_1
        > DDRSS_PHY_545, PHY_WDQLVL_PATT_2
        > DDRSS_PHY_801, PHY_WDQLVL_PATT_3

 

Improve write DQ training by increasing the minimum valid window to prevent false edge detection.
    - NOTE: This change is intended to address the same issue addressed by v0.6.1 (change 1) release.
                   It is recommended to implement both changes.
    - Register Updates (impacted parameters)
        > DDRSSn_PHY_32, PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
        > DDRSSn_PHY_288, PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
        > DDRSSn_PHY_544, PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
        > DDRSSn_PHY_800, PHY_WDQLVL_CLK_JITTER_TOLERANCE_3

 

Enable periodic ZQ calibration of the DRAM.
    - Register Updates (impacted parameters)
        > DDRSSn_CTL_229, ZQ_CALSTART_HIGH_THRESHOLD_F0
        > DDRSSn_CTL_229, ZQ_CALSTART_NORM_THRESHOLD_F0
        > DDRSSn_CTL_230, ZQ_CALLATCH_HIGH_THRESHOLD_F0
        > DDRSSn_CTL_233, ZQ_CALSTART_NORM_THRESHOLD_F1
        > DDRSSn_CTL_234, ZQ_CALLATCH_HIGH_THRESHOLD_F1
        > DDRSSn_CTL_234, ZQ_CALSTART_HIGH_THRESHOLD_F1
        > DDRSSn_CTL_238, ZQ_CALSTART_HIGH_THRESHOLD_F2
        > DDRSSn_CTL_238, ZQ_CALSTART_NORM_THRESHOLD_F2
        > DDRSSn_CTL_239, ZQ_CALLATCH_HIGH_THRESHOLD_F2
        > DDRSSn_CTL_267, ZQ_CAL_LATCH_MAP_1
        > DDRSSn_CTL_267, ZQ_CAL_START_MAP_1
        > DDRSSn_CTL_267, ZQ_CAL_LATCH_MAP_0
        > DDRSSn_CTL_267, ZQ_CAL_START_MAP_0

“

Based on the above changes, newly generated DTSI file with V0.9.1 of the tool was given by TI. With this new we generated U-boot for our custom board. Now we are not seeing the hang issue. It was booting properly in both the eMMC and xSPI modes. 

Please let us know whether the fix done in the DDR config file is good to go for our design. Or is there any chances that the same issue may reoccur. From the changes done in the DDR config file, is there any constraints to be taken care for the CA and CS drive strength settings 

I have attached the Processor-DDR schematics and updated DTSI file given by TI.

DDR schematics.pdf

SPRACU8A_Jacinto7_DDRSS_RegConfigTool.xlsm

Regards

Saravanakumar

  • 0
    TI__Intellectual 1400 points

    Hello,

    Is this thread still open ?

    Best Regards,

    Kelvin

  • 0 in reply to Kelvin Ayala
    TI__Mastermind 38170 points

    This issue (DDR instability) was resolved offline prior to this thread being opened. The understanding is that the open question (purpose of this thread) is:

    Saravanakumar Balasubramanian said:
    Please let us know whether the fix done in the DDR config file is good to go for our design. Or is there any chances that the same issue may reoccur. From the changes done in the DDR config file, is there any constraints to be taken care for the CA and CS drive strength settings

    When the original issue was brought to TI's attention, the customer's DTSI file was provided. TI reviewed the DTSI file, and found the issues described in this thread. There is no other known issue with the register settings. If the custom board adheres to the layout and routing guidelines (https://www.ti.com/lit/pdf/spracn9) , then there is no known reason which would prevent the DDR interface from functioning properly. However, customers should always adequately test their designs / applications in their intended environment.

    We are closing this thread - if additional help is needed , please re-open a new ticket.