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AM3352: Bring up Fail

Yu Bao
Prodigy 50 points

Part Number: AM3352

Hi,TI

    Design fobbiden RTC (RTC_PWRONRST=0; VDDS_RTC=RTC_KALDO_EN=1.8V; CAP_VDD_RTC=1.1V).

    SYSBOOT[15-0]=0100 0010 1111 0011

    USE KSZ8041 in RMII mode, external 50MHz Digital clock source(oscillator).

    

    1.UART0 continuous output "CCCC..."

    2.CLKOUT1 can not see any signal

     It seems Internal CLK have something wrong? And the power up sequence is OK? Further more, How to resolve the problem

Thanks

  • 0
    TI__Guru 63605 points

    It appears the device has a valid reference clock if UART0 is transmitting "CCCC..."

    The logic in the device that enables CLKOUT1 on the XDMA_EVENT_INTR0 pin is very simple, so not much to go wrong.

    I suspect the device is not latching a logic high on the LCD_DATA[5] pin, which is the SYSBOOT[5] input. Have you confirmed the LCD_DATA[5] pin is high on the rising edge of the PWRONRSTn pin?

    What components are connected to the LCD_DATA[5] pin?

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 50 points

    Hi,Peaves

       1. The picture shows, When PORZ Pin (B15) is rising, LCD_DATA[15] keeps 3V+.

       2. LCD_DATA[5] througt 10KΩ to 3.3V

       3. TFT_G0、TFT_G1 and some other pins also have 200kHz signal, it seems strange.

       4. If two projects have the same DDR、FLASH、ETHERNET PHY connect to the same pin of AM335x, while the PCB layout are difference. Are they can share the same software？

      

  • 0 in reply to Yu Bao
    TI__Guru 63605 points

    Please read the value of the following two registers so we can confirm the device latched the correct value on the SYSBOOT[5] input and the XDMA_EVENT_INTR0 pin was properly configured.

    control_status Register (offset = 40h), (0x44E10040)
    conf_xdma_event_intr0 Register (offset = 9B0h), (0x44E109B0)

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 50 points

    I am need some times to reseach how to do.could wait some times？thank you