TDA4VM: Got segmentation fault in PC inference

Amy Lian

Prodigy 10 points

Part Number: TDA4VM

Dear TI Team,

I have a resnet model with a custom layer as final layer.

When I generated inference results with a large image lists, It showed segmentation fault at specified frame.

It's fine at sdk7.3 and 8.2, but failure in sdk 8.4 .

I find the structure of sTIDL_Layer_t is different between sdk 8.2 and sdk 8.4 . Then I try to print the memory size (sysMems) in custom layer,

it seems that the memory will decrease continuously until it's out of memery.

Kindly let me know the cause for the error and also possible solution to fix it .

Amy

over 3 years ago

0 Anshu Jain over 3 years ago

TI__Guru 56820 points

Hi Amy,

I couldn't follow the question clearly:

Amy Lian said:
it seems that the memory will decrease continuously until it's out of memery.

Can you explain this more, which memory you talking about here which is decreasing continuously?

Regards,
Anshu

0 Amy Lian over 3 years ago in reply to Anshu Jain

Prodigy 10 points

Dear Anshu,

I add some printf functions in my custom layer to show the information of sysMems.

int32_t TIDL_customMyProcess(void * tidlHandle,

sTIDL_Layer_t *tidlLayer,

void *inPtrs[],

void *outPtrs[],

void *params,

void *dmaUtilsContext,

const sTIDL_sysMemHandle_t sysMems[TIDL_SYSMEM_MAX],

int32_t execMode

)

{

int32_t status = CUSTOM_SUCCESS;

printf("\n [DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = %d \n", sysMems[TIDL_SYSMEM_L1_SCRATCH].offset);

printf(" [DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = %d \n", sysMems[TIDL_SYSMEM_L1_SCRATCH].size);

printf(" [DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = %d \n", sysMems[TIDL_SYSMEM_L2_SCRATCH].offset);

printf(" [DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = %d \n", sysMems[TIDL_SYSMEM_L2_SCRATCH].size);

printf(" [DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = %d \n", sysMems[TIDL_SYSMEM_L3_SCRATCH].offset);

printf(" [DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = %d \n", sysMems[TIDL_SYSMEM_L3_SCRATCH].size);

printf(" [DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = %d \n", sysMems[TIDL_SYSMEM_DDR_SCRATCH].offset);

printf(" [DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = %d \n", sysMems[TIDL_SYSMEM_DDR_SCRATCH].size);

.....

}

Here is the log when I inference. I found that TIDL_SYSMEM_L3_SCRATCH is decreasing continuously.

user@f244d409e4b1:/home/user/tda4/tda4_sdk_8.4_j721e/tidl_j721e_8.4# make tidl_run

cd ti_dl/test && ./PC_dsp_test_dl_algo.out && cd ../../

Processing config file #0 : testvecs/config/infer/public/onnx/tidl_infer_model_8bit_sty2_cali7.txt
----------------------- TIDL Process with REF_ONLY FLOW ------------------------

# 0 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 40960
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 8278.25 .... ..... ... .... .....
# 1 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 40192
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 8197.61 .... ..... ... .... .....
# 2 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 39424
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7746.98 .... ..... ... .... .....
# 3 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 38656
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7684.70 .... ..... ... .... .....
# 4 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 37888
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7887.77 .... ..... ... .... .....
# 5 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 37120
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7588.57 .... ..... ... .... .....
# 6 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 36352
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7951.67 .... ..... ... .... .....
# 7 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 35584
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7922.51 .... ..... ... .... .....
# 8 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 34816
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7898.41 .... ..... ... .... .....
# 9 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 34048
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7699.85 .... ..... ... .... .....
# 10 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 33280
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7832.42 .... ..... ... .... .....
# 11 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 32512
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7980.51 .... ..... ... .... .....
# 12 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 31744
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7816.84 .... ..... ... .... .....
# 13 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 30976
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7674.61 .... ..... ... .... .....
# 14 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 30208
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7809.60 .... ..... ... .... .....
# 15 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 29440
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 8123.12 .... ..... ... .... .....
# 16 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 28672
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7757.55 .... ..... ... .... .....
# 17 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 27904
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7768.88 .... ..... ... .... .....
# 18 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 27136
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7709.79 .... ..... ... .... .....
# 19 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 26368
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7786.27 .... ..... ... .... .....
# 20 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 25600
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 8101.41 .... ..... ... .... .....
# 21 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 24832
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7751.16 .... ..... ... .... .....
# 22 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 24064
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7902.04 .... ..... ... .... .....
# 23 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 23296
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 8081.80 .... ..... ... .... .....
# 24 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 22528
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7915.85 .... ..... ... .... .....
# 25 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 21760
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7854.90 .... ..... ... .... .....
# 26 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 20992
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7717.59 .... ..... ... .... .....
# 27 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 20224
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7470.14 .... ..... ... .... .....
# 28 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 19456
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7908.96 .... ..... ... .... .....
# 29 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 18688
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7789.53 .... ..... ... .... .....
# 30 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 17920
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7784.14 .... ..... ... .... .....
# 31 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 17152
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7901.94 .... ..... ... .... .....
# 32 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7656.68 .... ..... ... .... .....
# 33 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 15616
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7836.35 .... ..... ... .... .....
# 34 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 14848
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7852.54 .... ..... ... .... .....
# 35 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 14080
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7614.13 .... ..... ... .... .....
# 36 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 13312
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7717.51 .... ..... ... .... .....
# 37 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 12544
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7873.45 .... ..... ... .... .....
# 38 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 11776
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7622.60 .... ..... ... .... .....
# 39 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 11008
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7780.69 .... ..... ... .... .....
# 40 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 10240
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7824.90 .... ..... ... .... .....
# 41 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 9472
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7679.08 .... ..... ... .... .....
# 42 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 8704
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7703.27 .... ..... ... .... .....
# 43 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 7936
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7710.47 .... ..... ... .... .....
# 44 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 7168
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7733.07 .... ..... ... .... .....
# 45 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 6400
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 8138.01 .... ..... ... .... .....
# 46 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 5632
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7686.45 .... ..... ... .... .....
# 47 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 4864
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7621.51 .... ..... ... .... .....
# 48 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 4096
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7993.37 .... ..... ... .... .....
# 49 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 3328
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7904.54 .... ..... ... .... .....
# 50 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 2560
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7704.11 .... ..... ... .... .....
# 51 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 1792
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7844.12 .... ..... ... .... .....
# 52 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 1024
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7571.55 .... ..... ... .... .....
# 53 . ..
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L1_SCRATCH.size = 16384
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L2_SCRATCH.size = 457728
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_L3_SCRATCH.size = 256
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.offset = 0
[DEBUG] TIDL_SYSMEM_DDR_SCRATCH.size = 524544
T 7995.48 .... ..... ... .... .....
# 54 . ../bin/sh: line 1: 30523 Segmentation fault (core dumped) ./PC_dsp_test_dl_algo.out
makefile:388: recipe for target 'tidl_run' failed
make: *** [tidl_run] Error 139

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TDA4VM: Got segmentation fault in PC inference