Other Parts Discussed in Thread: TFP410
Hello,
We are trying to drive a TFP410 serializer chip from a custom AM62x processor. We are running the following modetest command:
root@am62xx-evm:~# modetest -M tidss -s 39:1920x1080@RG24
setting mode 1920x1080-60.00Hz@RG24 on connectors 39, crtc 37
When we look at the VOUT0_HSYNC and VOUT0_VSYNC signals for the device, we see valid timing pulses, so it appears the device is running in the proper mode, and when we dump the clock tree (cat /sys/kernel/debug/clk/clk_summary) the related clock appears to be configured to run at a sane rate (148.5 MHz)
...
clk:186:2 1 1 0 148529411 0 0 50000
...
However, we do not see anything on the VOUT0_PCLK pin on the board. We have checked for shorts, etc. It seems that the CLK pin is somehow gated or disabled. Can you help troubleshoot?
Our devicetree looks very similar to the TI provided SDK, we are using the same pinmux for the DSS controller for the parallel output and have confirmed the compiled DTB is consistent between the reference design and our design. I can supply the DTB / DTS file if it is helpful.
Thanks.
Mike
