Hi,
We are starting to put our custom kernels on the TDA4 DSPs (C66s, C7x).
To ensure fast memory access, we plan to use the strategy of the example vision_apps/apps/basic_demos/app_c7x_kernel/c7x, which is:
- Allocate memory in L2 SRAM for inputs and outputs
- DMA from target_ptr to allocated L2 SRAM
- Compute using L2's SRAM buffers
- DMA output from L2 SRAM to target_ptr
That part seems straight-forward. Where we have doubts is when reading the documentation of TIVX_MEM_INTERNAL_L2, which is passed to tivxMemAlloc():
tivxMemAlloc() API will linearly allocate from this memory
segement. After each allocatation an internal
offset will be incremented.
tivxMemFree() resets this offset to zero.
i.e tivxMemAlloc() and tivxMemFree() are not heap like memory
alloc and free functions.
Q1. Allocation/Deallocation behavior
- Does that mean that any call to tivxMemFree() deallocates every previously allocated segment? e.g.:
ptr1 = tivxMemAlloc(size1, TIVX_MEM_INTERNAL_L2);
ptr2 = tivxMemAlloc(size2, TIVX_MEM_INTERNAL_L2);
ptr3 = tivxMemAlloc(size3, TIVX_MEM_INTERNAL_L2);
tivxMemFree(NULL, 0, TIVX_MEM_INTERNAL_L2);
- Or does that mean that allocated memory should be deallocated in a FILO manner? e.g.:
ptr1 = tivxMemAlloc(size1, TIVX_MEM_INTERNAL_L2); // 1
ptr2 = tivxMemAlloc(size2, TIVX_MEM_INTERNAL_L2); // 2
ptr3 = tivxMemAlloc(size3, TIVX_MEM_INTERNAL_L2); // 3
tivxMemFree(ptr3, size3, TIVX_MEM_INTERNAL_L2); // 3
tivxMemFree(ptr2, size2, TIVX_MEM_INTERNAL_L2); // 2
tivxMemFree(ptr1, size1, TIVX_MEM_INTERNAL_L2); // 1
- What would happen if the proper order is not respected? e.g.:
ptr1 = tivxMemAlloc(size1, TIVX_MEM_INTERNAL_L2); // 1
ptr2 = tivxMemAlloc(size2, TIVX_MEM_INTERNAL_L2); // 2
ptr3 = tivxMemAlloc(size3, TIVX_MEM_INTERNAL_L2); // 3
tivxMemFree(ptr1, size1, TIVX_MEM_INTERNAL_L2); // 1
tivxMemFree(ptr2, size2, TIVX_MEM_INTERNAL_L2); // 2
tivxMemFree(ptr3, size3, TIVX_MEM_INTERNAL_L2); // 3
Q2. Thread-safety
From my understanding (and please correct me if I'm wrong), each target kernel is running on a separate thread on its target. Since we are putting more than one kernel on a DSP, and we want to use L2SRAM, we fear there may be conflicts when running two DSP kernels in parallel. What is the behavior of two threads on the DSP concurrently allocating and deallocating from L2 SRAM through tivxMemAlloc()/tivxMemFree()?
Thank you,
Fred
