AM4379: CS0 not asserted in SPI boot

Hello Sasami,

Thank you for the query.

Has customer tried toggling the pin configuring as a port.

Sh.Sasaki said:

Since it may be a hardware problem, please tell me what to check with the hardware.

Is this a custom hardware?

Would customer want to share the schematics or do a self-review?

Regards,

Sreenivasa

Hi Sreenivasa-san,

Kallikuppa Sreenivasa said:

Has customer tried toggling the pin configuring as a port.

They haven't tried any other pins.

Kallikuppa Sreenivasa said:

Is this a custom hardware?

Yes.

Kallikuppa Sreenivasa said:

Would customer want to share the schematics or do a self-review?

I will check with them.

Additional information was provided by the customer.
This problem occurs when they power up the FPGA on board.
Once they power up the FPGA, the SPI CS won't work after that.
If the board has never been powered on to the FPGA, the SPI CS will work.

Best regards,
Sasaki

Hello Sasami,

Thank you for the inputs.

Sh.Sasaki said:

Additional information was provided by the customer.
This problem occurs when they power up the FPGA on board.
Once they power up the FPGA, the SPI CS won't work after that.
If the board has never been powered on to the FPGA, the SPI CS will work.

This looks to be more of a system level issue. Please check if the FPGA pin is an input and if the IO level are same.

Is there a series resistor and is the value ~33R

Regards,

Sreenivasa

Hi Streen-san,

Thank you for your comment.

There is no series resistance between FPGA and Sitara.

I wiill check the IO level.

Also, they provided me with a schematic, so I will send the file to you in a private message.

Best regards,
Sasaki

Hello Sasami,

Thank you for the inputs.

I can do a quick review.

Regards,

Sreenivasa

Hello Sasami,

Thank you for the inputs.

I did a quick check and observed that the SPI flash is connected to only the AM437x.

I am assuming the issue may be with the bootmode configuration pins being connected to the processor and the FPGA.

I am not able to verify that with the provided schematics.

Can you please request customer to check if the FPGA port connected to the bootmode pins have any terminations internally that have been enabled.

If yes, customer will have to analyze the effect of the boormode pin and make the changes accordingly.

Regards,

Sreenivasa

Hello Sreenivasa-san,

Thank you for your supoort.

Kallikuppa Sreenivasa said:

Can you please request customer to check if the FPGA port connected to the bootmode pins have any terminations internally that have been enabled.

If yes, customer will have to analyze the effect of the boormode pin and make the changes accordingly.

I cheked this with my customer.

They checked the voltage between the FPGA and the AM437x and it was what they expected.

They also checked the AP register via JTAG and SYSBOOT was set correctly.
Is there anything else we should check?

Best regards,
Sasaki

Hello Sasaki, 

Thank you.

Would it be possible for customer to capture the bootmode pin status when the reset is released. The latching happens during reset transition.  

When is the FPGA being configured?

Regards,

Sreenivasa

Hello Sreenviasa-san,

Thank you for your support.

Kallikuppa Sreenivasa said:

Would it be possible for customer to capture the bootmode pin status when the reset is released. The latching happens during reset transition.  

When is the FPGA being configured?

I have confirmed the above with my customer.

They checked the voltage on SYSBOOT when the RST was released and everything was as expected.

RST & SYS17 Waveform

RST & SYS18 Waveform

The power-up sequence is as follows.

1. Power on FPGA
2. Configuration
3. Power on AM437x after confirming INIT_DONE of FPGA
4. Release RST of AM437x after 1 second

Also, as a test, they turned on only the AM437x on another board (which has been confirmed to be working properly), but CS was not output as in the above symptoms.SYSBOOT is powered.
The AM437x will not start unless power is supplied with peripheral ICs and other pull-up resistors connected.

Do you know the reason for the above?

Best regards,
Sasaki

Hello Sasaki,

Thank you for the inputs.

Sh.Sasaki said:

Also, as a test, they turned on only the AM437x on another board (which has been confirmed to be working properly), but CS was not output as in the above symptoms.SYSBOOT is powered.
The AM437x will not start unless power is supplied with peripheral ICs and other pull-up resistors connected.

Do you know the reason for the above?

I am not sure about the peripherals and hence could provide some guidelines. If there are any of the peripherals resetting the processor or providing clock, i assume these have to be operational.

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your support.

Kallikuppa Sreenivasa said:

I am not sure about the peripherals and hence could provide some guidelines. If there are any of the peripherals resetting the processor or providing clock, i assume these have to be operational.

I confirmed them with my cusotmer.

They have verified that the processor reset and clock are working correctly.

Is there anything else they should check?

Best regards,
Sasaki

Hello Sasaki, 

Thank you for the inputs.

You mentioned the below power sequwnce

The power-up sequence is as follows.

1. Power on FPGA
2. Configuration
3. Power on AM437x after confirming INIT_DONE of FPGA
4. Release RST of AM437x after 1 second

Couple of questions i can think

Is there a reason for FPGA has to be on first. Would it be able for customer to revere the sequence?

As you mentioned, this issue is observed only when the FPGA is powered. You also measured the boot voltages seems Ok.

I need to check internally with the team on the system level issue being seen by customer.

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your support.

Kallikuppa Sreenivasa said:

Is there a reason for FPGA has to be on first. Would it be able for customer to revere the sequence?

This is because the customer base does not allow access to NAND from the AM437x when the FPGA is turned off.

Also, they are using the TPS65218D0PHPR with default settings so I think the power sequencing is fine. (There is no problem in operation with the current board)

Best regards,
Sasaki

Hello Sasaki

I do not have any quick suggestion.

I am checking with internal experts and will update you.

Regards,

Sreenivasa

Hello Sreenivasa-san,

Thank you for your reply.

Please let me know if you have any additional information.

Best regards,
Sasaki

Hello Sasaki

Thank you for checking.

I do not have any inputs to share.

I am not sure how we could take this forward. Let me review with experts one more time.

Regards,

Sreenivasa

Hi Sreenivasa-san,

Do you have any update?

Best regards,
Sasaki

Hello Sasaki

Thank you for checking. Sorry for not being able to help on this issue.

I do not have any inputs. Will follow-up one more time.

Regards,

Sreenivasa

Hello Sasaki

Please check if this thread could help.

Regards,

Sreenivasa

Hello Sreenivasa-san,

Thank you for your support.

I will check it.

Best regards,
Sasaki

Hello Sasaki

Noted and thank you.

Regards,

Sreenivasa