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Frame Synchronization

I'm a member of Brazil-IP(http://www.brazilip.org.br/) and I'm developing a TMS320C6202 DMA Controller and I'd like to know about the steps executed by it when it's configurated as following:

- FS = 1;

- FSIG = 0;

Since the Frame Synchronization is enabled and a new synchronization event arrives while the last frame is still being transferred,  what happens?

Will the last transfer be ignorated? or it will keep doing the last transfer starting from the last element...?

 

 

  • Section 2.4.2 of the TMS320C620x/C670x DSP Program & Data Memory Controller/DMA Controller Ref.Guide  (SPRU577) discusses how the sync event is cleared when configured for Frame Synchronization.

    Clearing frame synchronization condition : Frame synchronization clears the RSYNCSTAT field when the DMA completes the request for the first read transfer in the new frame.