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DSP output from "release" does not consist with "whole_program"

Steve Yeh
Intellectual 380 points


Dear all, 

 

Is there any document decript the details of the compiler profile in coedc engine "release" and "whole_program"?

I am porting a pattern recognition algorithm on DSP and facing a problem that the system accuracy of "release" does not consist with "whole_program".

The accuracy is 90%(average time 61ms) in "release" mode, but be decreased to 46%(58ms) in "whole_program" profile.

 

By the way, how can i get the DSP clock rate from my 8168EVM?

I try to use CLK_countspms in the codec program, and it returns 800000.

Is this reliable or it just shows the DSP/BIOS setting value, may not be the real clock rate.

 

Steve

  • 0
    Genius 4375 points

    Hi Steve,

    Which version of DSP/BIOS or SYS/BIOS are you using?  SYS/BIOS 6.32.00 (and later) offers better-optimized 'release' builds whose performance should be comparable to whole_program[_debug].  Prior to this SYS/BIOS release, performance was more comparable to the 'debug' build (not optimized at all).  

    Yes, BIOS CLK/Clock APIs return the frequency that BIOS "knows" about (i.e. configured with).   To find the actual frequency you could calculate the difference in values of the TSCL and TSCH registers and compare this to the expected difference after halting the core after a fixed amount of time (i.e. 30 seconds) measured using a stopwatch.  These registers increment at the CPU frequency and are usually the best tool when trying to figure out the actual CPU frequency.

    Regards,

    Shreyas

  • 0 in reply to Shreyas Oppanthaya
    Intellectual 380 points

    Shreyas,

    I update tool-chain to SYS/BIOS 6_32_01_38, but get the same result.

    Thanks a lot.