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FPGA and DSP communication using SRIO

Renaissance
Intellectual 925 points

I have a question of the FPGA (SRIO core IP) and DSP connection. I am wondering if you can get some help on it.

From FPGA->DSP, we will firstly use the burst write using Direct IO in SRIO, which will be very similar as the SRIO_slave.c code in the C6455EVM example, in which the DSP2 will be initialized to be waiting for data writing from DSP1. Here I just replace the DSP1 by FPGA as the master. The FPGA will know the DSP ID and the memory address, where the data will be sent to.

However, I also want to test the DSP->FPGA communication. Because the DSP should send the ID and memory address to FPGA information and then FPGA can initialize the data transferring.  I hesitate to use the similar method as defined in SRIO_master.c, because the target is FPGA, which is not DSP. So the target address will be impossible to set for LSU REG.  So, how could I make the DSP->FPGA message passing?

Thank you very much,

  • TI__Guru* 84110 points

    The SRIO logic in the FPGA must have a defined address or else it must be designed to only accept broadcast transmissions. Most likely, you have a hard-coded or register programmed target ID.

    Similarly, the SRIO logic in the FPGA will be designed to use the destination address to decide where to send the data that it receives. Whether it is purely memory-mapped or some other method of mapping the destination address from the SRIO packet into a destination within the FPGA or even outside the FPGA.

    It will be very correct to use some of the SRIO_master.c file and protocol. If you do not wish to implement all of the same features in the FPGA, then some of the code could be removed.

    Regards,
    RandyP