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AM625: LVCMOS Digital Clock Source

Lawrence Wong
Genius 16820 points

Part Number: AM625

Customer have question regarding the MCU_OSC0_XI input.  They plan to use and LVCMOS oscillator, but it looks like for the application were are limited by the fact the oscillator output can only run as low as 2.5V.  They cannot change that due to some supply constraints at the moment.  From reading the spec, it looks like this signal is internally AC-coupled. Any concern about using a resistor divider to level shift from 2.5V to 1.8V?

Also any concern to the rise/fall times the MCU_OSC0_XI input as the datasheet does not have it spec’d and when they are thinking of putting a resistor divider here.

  • 0
    TI__Guru 64655 points

    They should be able to use a resistor divider as long as the source impedance of their resistor divider is low enough that it can drive MCU_OSC0_XI pin with the appropriate rise/fall times. The 1.8V signal swing should be 10% to 90% rise or 90% to 10% fall in less than 8ns.  A faster rise/fall is better, as it will reduce clock jitter on the internal reference clock.

    Regards,
    Paul 

  • 0 in reply to peaves
    TI__Guru 64655 points

    I forgot to mention a couple of other points.

    The clock they source should not exceed a 45%/55% duty cycle. 

    We do not recommend using an LVCMOS oscillator that utilizes a PLL to generate its clock output. If so, they need to make sure the clock it sources has less than 10ps of RMS period jitter over 100k samples, 100ps of peak-to-peak period jitter over 100k samples, or 2ps of RMS random phase jitter.

    Regards,
    Paul 

  • 0 in reply to peaves
    TI__Genius 16820 points

    HI Paul,

    Follow up question from customer:  

    ------------------------

    Looking at our XO spec.

     

    Looks like we have an RMS Phase Jitter of 2.5ps max (integrated from 12khz to 20Mhz).  Is there an integration period of the 2ps RMS phase jitter?  What kind of issue may we run into by not meeting the RMS phase jitter spec?

    ------------------------

    Regards,

    Lawrence

  • 0 in reply to Lawrence Wong
    TI__Guru 64655 points

    I do not follow your question about "our XO spec".  Please provide more details.

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Genius 16820 points

    From customer:

    Yes, its possible I misunderstood the random phase jitter.  You mentioned that we should have below “2ps of RMS random phase jitter”. Our XO only specs the RMS phase jitter, I’m assuming this is the same spec as the RMS random phase jitter you are describing.  Since our XO specs the RMS phase jitter integrated over 12k to 20Mhz I was wondering if the 2ps limit is also over the same integration period.  Also, since we don’t quite meet the 2ps spec it looks like we will need to find an alternative.  Will using this XO for an initial build be a big risk for the AM62x’s internal PLL, should we be worried about the processor boot up or maybe just risk having a timing issue for say the RGMII interface or LPDDR?

  • 0 in reply to Lawrence Wong
    TI__Guru 64655 points

    I will need to try to dig up some old emails that discussed the 2ps limit mentioned in my previous reply. I don't remember the details of the limit, but thought we considered the TI solution.

    It may be difficult to get answers related to this question until after the holidays if my old emails do not provide enough details for me to answer the question.

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Guru 64655 points

    I do not anticipate an issue with a source that has 2.5ps of random jitter integrated 12kHz to 20MHz. We selected 2.0ps as a recommendation after evaluating the performance of many LVCMOS oscillators.

    It is very difficult for TI to select a firm limit for this parameter since there are many system-level contributors like power supply noise and specific PLL configuration that influence device performance. Therefore, we recommend customers validate their system across the full range of expected operating conditions for any reference clock solution.

    Regards,
    Paul