TMS320C6657: UART DMA Event Data Invalid

Mari Tsunoda,

Just to narrow down the problem, on the first hand, Please check whether the "uart -dma test example" given in the "Processor SDK - Software Package" works fine on the board.

By  the way, they use the custo board ? or the TI-C6657 EVM board? 

If by any chance, they have the TI-C6657EVM as the reference board, I would recommend them to run the UART-sample-program on the EVM first and then move on to the custom board.

It is always good to start with something already working.

To run the Uart program on C6657 EVM, please follow the steps given here: 

[FAQ] TMS320C6657: UART Example project for C665x family devices - Processors forum - Processors - TI E2E support forums

Regards

Shankari G

Hi Shankari,

I am checking now and will get back to you.

Best,

Mari

Sure Mari.

No urgency. I can keep waiting.

Let me know, how it goes for you, once you are done with your experiments.

With your permission, changing the status of this thread as "Waiting".

Regards

Shankari G

Hi Shankari,

I checked with my customer and they are using a custom board. Their UART is working normally in their program except for the situation in the post.

Best,

Mari 

Mari,

If you look into the video in the link, I posted above, It is example of "UART with EDMA". 

That is the working example, Which I personally tested on the C6657 device, on the TI-C6657 EVM.

Which means, that can be used as a referene code to make the "uart and EDMA" to work, hand-in-hand, without any errors with "valid subsequent data".

--

Please ask customer to compare their custom code sequence with this example code-sequence; And find the difference.

Once the difference is found, they can integerate that portion of the code for their custom board.

Link to download the code: PROCESSOR-SDK-RTOS-C665x 06_03_00_106 -- http://software-dl.ti.com/processor-sdk-rtos/esd/C665x/latest/index_FDS.html

How to get started and play around with the example code: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1080748/faq-tms320c6657-quick-start-guide-c6657-and-c6657-evm

  Regards

Shankari G

Hi Shankari,

Can you tell me what would happen if unexpected data were to be received? What happens to the UART FIFO and DMA event?

I will ask them to compare their code.

Best,

Mari

Mari

Mari Tsunoda said:

Can you tell me what would happen if unexpected data were to be received? What happens to the UART FIFO and DMA event?

Let me have a closer look and get back in a day or two.

And also,

Let me forward your queries to internal team.

And also, due to new year holidays,  please expect a delayed response.

Regards

Shankari G 

Mari Tsunoda said:

Can you tell me what would happen if unexpected data were to be received? What happens to the UART FIFO and DMA event?

If unexpected data were to be received, we need to check what kind error status are getting set.

For example, whether it is an over-run error or parity error or framing error or a break ? Accordingly, the error handling has to be done.

First of all, whether the UART - FIFO is interrupt mode or POLL mode?

If it is interrupt mode, follow the instructions given in section 2.5.3.1 in https://www.ti.com/lit/ug/sprugp1/sprugp1.pdf 

or

otherwise, section 2.5.3.2 for POLL mode in

https://www.ti.com/lit/ug/sprugp1/sprugp1.pdf 

Regards

Shankari G

Hi Shankari,

Thanks for your response. They still want the procedure to reset UART FIFO state and EDMA event below to be checked? Could you review the below procedure for me? (Note that there are differences between the procedure in the original post and below, please check the one below)

①UART LSR read (to check for UART errors)
②UART RBR read 16 times or until LSR DR bit is 0 (to clear UART Parity, Framing, Overrun)
③UART PWREMU_MGMT register URRST set to 0
④UART PWREMU_MGMT register UTRST set to 0
⑤UART FCR set to 0x0000000F
⑥UART PWREMU_MGMT register URRST set to 1
⑦UART PWREMU_MGMT register UTRST set to 1
⑧EDMA EECR bit 4 set to 1　
⑨EDMA EMCR bit 4 set to 1
⑩EDMA SECR bit 4 set to 1
⑪EDMA ECR bit 4 set to 1

Best regards,

Mari Tsunoda

Mari,

Which mode, your UART FIFO is used? Interrupt mode or Poll mode? Accordingly, the procedure might change. Please do reply..

I could review the reset procedure of UART FIFO and EDMA event and get back.

As your software design and your board is not known to me, though, I do it, it would be only theoritical. 

You will be the apt person to check the error status on the real hardware environment and include the error handling mechanism according to your output observations etc...

Regards

Shankari G

Hi Shankari,

Thanks for your quick response. I will check will with my customer and get back to you.

Best,

Mari

ok

Hi Shankari,

FIFO is in Poll Mode.

Regards,

Mari

Hi Shankari,

Any update on this?

Best regards,

Mari Tsunoda

Mari Tsunoda said:

②UART RBR read 16 times or until LSR DR bit is 0 (to clear UART Parity, Framing, Overrun)
③UART PWREMU_MGMT register URRST set to 0
④UART PWREMU_MGMT register UTRST set to 0
⑤UART FCR set to 0x0000000F
⑥UART PWREMU_MGMT register URRST set to 1
⑦UART PWREMU_MGMT register UTRST set to 1
⑧EDMA EECR bit 4 set to 1　
⑨EDMA EMCR bit 4 set to 1
⑩EDMA SECR bit 4 set to 1
⑪EDMA ECR bit 4 set to 1

⑥UART PWREMU_MGMT register URRST set to 1
⑦UART PWREMU_MGMT register UTRST set to 1

UART PWREMU_MGMT register FREE set to 1  ----> Free running mode is also to be enabled.

============

"Free-running enable mode bit.

This bit determines the emulation mode functionality of the UART.

When halted, the UART can handle register read/write requests, but does not generate any transmission/reception, interrupts or events.

0 = If a transmission is not in progress, the UART halts immediately. If a transmission is in progress, the UART halts after completion of the one-word transmission.

1 = Free-running mode is enabled. UART continues to run normally." 

============

In this sequence,

PWREMU_MGMT - Power and Emulation Management Register - the 0th bit- that is "FREE" field should also get set to 1.

#define CSL_UART_PWREMU_MGMT_UTRST_MASK                         ((uint32_t)0x00004000U)

#define CSL_UART_PWREMU_MGMT_URRST_MASK                         ((uint32_t)0x00002000U)

#define CSL_UART_PWREMU_MGMT_FREE_MASK                          ((uint32_t)0x00000001U)

/*
** Values used to configure the power and emulation management register.
*/
#define UART_PWREMU_MGMT_ENABLE (CSL_UART_PWREMU_MGMT_UTRST_MASK | \
CSL_UART_PWREMU_MGMT_URRST_MASK | \
CSL_UART_PWREMU_MGMT_FREE_MASK)

/* Reset and enable UART TX/RX in free-running mode */
UART_pwremuConfig_v0(baseAddr, UART_PWREMU_MGMT_ENABLE);

======

Additionally, you can also refer to the code snippets on the Line status error with dma mode.

C:\ti\pdk_c665x_2_0_16\packages\ti\drv\uart\src\v1\UART_v1.c

static inline void UART_procLineStatusErr(UART_Handle handle)
{
    UART_V1_Object     *object = (UART_V1_Object*)handle->object;
    UART_HwAttrs const *hwAttrs = (UART_HwAttrs const *)handle->hwAttrs;
    uint32_t            lineStatus;

    if (object->readSize > 0U)
    {
        lineStatus = UARTReadStatus(hwAttrs->baseAddr);

        if (((lineStatus & UART_FIFO_PE_FE_BI_DETECTED) == UART_FIFO_PE_FE_BI_DETECTED) ||
            ((lineStatus & UART_OVERRUN_ERROR) == UART_OVERRUN_ERROR))
        {
            /* empty the RX FIFO which contains data with errors */
#ifdef UART_DMA_ENABLE
            if (hwAttrs->dmaMode == TRUE)
            {
                /* Disable DMA RX channel */
                UART_disableDmaChannel(handle, (bool)false);

                if (object->readTrans != NULL)
                {
                    object->readTrans->count = 0;
                }
                else
                {
                    object->readCount = 0;
                }
            }
            else
#endif
            {
                if (object->readTrans != NULL)
                {
                    object->readTrans->count = (uint32_t)(object->readCount);
                }
            }
            /* dummy read, clear the RX line status interrupt */
            (void)UART_v1_readData(handle, (int32_t)(object->readSize));
            UARTIntDisable(hwAttrs->baseAddr, UART_INT_RHR_CTI | UART_INT_LINE_STAT);

            /* Reset the read buffer and read count so we can pass it back */
            object->readBuf = (uint8_t *)object->readBuf - object->readCount;

            if (object->readTrans != NULL)
            {
                if ((lineStatus & UART_BREAK_DETECTED_ERROR) != 0U)
                {
                    object->readTrans->status = UART_TRANSFER_STATUS_ERROR_BI;
                }
                else if ((lineStatus & UART_FRAMING_ERROR) != 0U)
                {
                    object->readTrans->status = UART_TRANSFER_STATUS_ERROR_FE;
                }
                else if ((lineStatus & UART_PARITY_ERROR) != 0U)
                {
                    object->readTrans->status = UART_TRANSFER_STATUS_ERROR_PE;
                }
                else
                {
                    object->readTrans->status = UART_TRANSFER_STATUS_ERROR_OE;
                }
            }

            /* Call back to application if in callback mode */
            UART_v1_callback(handle, (bool)true);
            object->readTrans = NULL;
        }
    }
}

------

The rest, seems to be fine.

⑧EDMA EECR bit 4 set to 1　
⑨EDMA EMCR bit 4 set to 1
⑩EDMA SECR bit 4 set to 1
⑪EDMA ECR bit 4 set to 1

Regards

Shankari G

Hi Shankari,

Great! Will send this to my customer and see their response.

Best regards,

Mari

OK.

Hi Shankari,

Great! Thanks for your quick response.

Best regards,

Mari Tsunoda