TDA4VM: nested interrupt on R5F

Tony Tang

Part Number: TDA4VM

In the PDK user guide declared nested interrupt not supported on R5F. is it a limitation of R5F interrupt controller or TI did not implement the feature?

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_04_00_06/exports/docs/pdk_jacinto_08_04_00_21/docs/userguide/jacinto/modules/freertos.html

4.2.3. Features Not Supported

Co-routines, stream buffer are not enabled and compiled by default. Users can add these to the FreeRTOS config and makefile if they want to use these features.
Tickless IDLE mode
Task level memory protection wrapper
On R5F, nested interrupts are not supported.
HW Interrupt and SW Interrupt Load measurements are not supported.

In the TRM, R5F support priority interrupt, can it be used for interrupt nest?

• Integrated vectored interrupt manager (VIM)
– 512 interrupts per core
• Only interrupts connected to R5F core 0 are available in lock mode
• Each interrupt programmable as either IRQ or FIQ
• Each interrupt has a programmable enable mask
• Each interrupt has a programmable 4-bit priority
– Priority interrupt supported

over 3 years ago

0 Brijesh Jadav over 3 years ago

TI__Guru**** 484335 points

Hi Tony,

Please check below link, especially i2132 errata.

https://www.ti.com/lit/er/sprz455c/sprz455c.pdf?ts=1671793217826&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTDA4VM

Regards,

Brijesh

0 Tony Tang over 3 years ago in reply to Brijesh Jadav

TI__Mastermind 29612 points

Brijesh,

Thanks.

regarding the workaround,

Alternatively, user can implement a completely SW managed interrupt servicing scheme, where every ISR (Interrupt Service Routine) shall check for the presence of an active higher priority interrupt (by reading Interrupt Raw Status registers in VIM) and jumping to the ISR corresponding to that interrupt.

How can this be implemented? If already in ISR handing a interrupt, should not know there is new higher priority interrupt coming.

0 Brijesh Jadav over 3 years ago in reply to Tony Tang

TI__Guru**** 484335 points

Well, i think its difficult and can increase ISR overhead, because then it requires ISR to check for higher priority interrupt on every statement in the ISR.

Typically we dont use nested interrupt, any specific reason customer would like to use nested interrupts?

Regards

Brijesh

Processors

Processors forum

TDA4VM: nested interrupt on R5F

4.2.3. Features Not Supported