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AM6411: eMMC memory sharing between two processors

A V
Prodigy 40 points
Part Number: AM6411

Hi there!

In my architecture, I have an ultra low power processor, as well as a main processor (TI AM6411). I am using an eMMC card, which is interfaced with the ultra low power processor for storing data memory.

However,  I require memory storage element which needs to be connected to my AM6411 processor too.

Is it possible to interface the same eMMC memory chip with both the ultra low power processor and main processor (TI AM6411)?

So that if possible, I could save on having two memory chips for the two processors, and use a single eMMC card with both.

 

  • 0
    TI__Guru* 87095 points

    Hello A V,

    I am not familiar with this usecase. Is there a specific EMMC you are looking at that is marketed as compatible with multiple masters?

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Prodigy 40 points

    Hi Nick,

    The part number of the eMMC we have chosen is S40FC004C1B2I00000. I believe compatibility with multiple masters would not be an issue, as at any single point of time, only one host will be communicating with the eMMC card. We don't have a use case when both master hosts would interact with the eMMC simaltaneously.

    In our application we would want to transmit the data from the eMMC card, to our Ethernet port which is interfaced with the main processor as soon as possible. Currently, in our architecture, an ultra low power processor communicates with the eMMC. Hence, data flow is : eMMC card -> Ultra Low Power Processor -> Main processor ->Ethernet

    However, it is taking a lot of time

    Hence, we are exploring the option of having the main processor (which is interfaced with Ethernet) as well as the Ultra Low Power microcontroller  communicate with the eMMC card. Only one host interacts with the eMMC card at once.

  • 0 in reply to A V
    TI__Guru* 87095 points

    Hello A V,

    First, let me set some support expectations. Then, I'll discuss some other subjects.

    Support limitations 

    This is not a usecase that TI is able to support. To the best of my knowledge nobody at TI has tested or validated this usecase (I am double checking, but most of my team is on vacation until January). So I cannot tell you whether the usecase is technically possible. And if the usecase is technically possible, I cannot answer questions to help you to get it working.

    Other discussions 

    Even if the peripheral is INSIDE the AM64x (instead of outside the AM64x, like an EMMC), TI only supports one processor core owning the peripheral at a time. E.g., to send information over a CPSW Ethernet port, either Linux can own the CPSW, or an R5F core can own the CPSW. We do not support both Linux and an R5 core directly talking to the CPSW at the same time.

    I believe this is mostly due to coordination issues. Which core initializes the peripheral? What if one core overwrites settings & memory that the other core set? What if both cores try to access the peripheral at the same time, or one core grabs received data that was meant for the other core, or timing requirements for a protocol get missed because one core is waiting on the other core to do something, or... etc.

    It is possible to set up shared memory regions in DDR or within the AM64x internal memory, so it may also be possible to set up a shared memory region in an external EMMC, where the memory is shared with an external processor instead of another processor core. I cannot say for sure.

    What would I research next if I were you?

    First, I would check to see if the EMMC protocol even supports multiple host controllers. The protocol itself may break if multiple hosts try to use the same protocol bus. When I think about protocols like I2C, multimaster is explicitly enabled by the protocol.

    Next, you would need to figure out a way to make sure that the microcontroller and the AM64x could properly coordinate accesses. The obvious coordination is some kind of interrupt setup so one core knows when data from the other core is ready, but you may need to coordinate a bunch of other things as well (for examples, see the "other discussions" section above). That might require custom drivers for one or both of the processors that are getting used.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Guru* 87095 points

    If a shared EMMC does not work, there may also be other ways to speed up the sending of data to the Ethernet interface .

    e.g., could the microcontroller just write the data that needs to get sent to the AM64x at the same time that it is writing that data to the EMMC? (presumably the data on the EMMC that needs to get transferred was initially written there by the microcontroller). etc.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Guru* 87095 points

    Some additional info from one of our hardware engineers:

    I'm not aware of this being an option [i.e., multiple hosts] in the eMMC or SD Card standards.  Even is supported, the data transfer speed would be very restricted due to signal integrity issues that result from having stubs on the PCB traces.  We only allow a single device to be connected on most of our high speed interfaces since point-to-point connections are required to maintain good signal quality.

    Regards,

    Nick