TDA4VL Overview Questions (Compilers, Scheduling, Constraints)

Hello Radek,

Please provide more detail, what device/processor are you using?  

Thank you,

~Leonard  

Hi Leonard, I believe this is for the TDAVlow/mid

Hello, is there any progress? or more details needed?

Hi Radek,

Yes, please, I think more details would be helpful so the right team can be involved, 

~Leonard 

Please share more details to help you further.

Regards,

Brijesh

we're interested for info about processor TDA4VL

Hello, are there any news?

Hello Radek,

Could you please share the questions shared previously? I don't have access to these.

Let me post here to start the conversation all of the resources you need to get started with the EVM.

Here is the link to the TDA4VL device on ti.com. You can find datasheets, TRM, schematics and other relevant information:

https://www.ti.com/product/TDA4VL-Q1

Then, to download the SDKs for this device, please find them here:

https://www.ti.com/tool/PROCESSOR-SDK-J721S2

Radek Wiltschko said:

What are the constrains of the cores?

How to schedule them?

How transfer data among the cores?

I'll need some background for this question, what are you trying to run here?

Radek Wiltschko said:

Programing? What are the compilators? How to check the code? How to debug?

We provide compilers for some of our cores, for example the R5F cores. And debugging is supported through Code Composer Studio (CCS). Other cores we reference other compilers, such as for the A72 cores (Linux). Which cores are going to be used here?

Regards,

Erick