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TDA4VM: OSPI - OCTAL MODE READ NOT WORKING

Part Number: TDA4VM
Other Parts Discussed in Thread: DRA821

Hello,

We have implemented OSPI driver on our own.

Reading in Extended SPI mode is working successfully but when we switch to OCTAL SPI mode it is not working to read.

We tested reading only so far.
In PIC. 1. the flash command list can be found for Extended SPI and Octal SPI commands.
  
PIC.1

Below you can find two examples:
Example 1.  "read volatile configuration register"  in Octal Mode
In the PIC.2 you can find the OSPI Registers configuration accordingly to the list above to "READ VOLATILE CONFIGURATION REGISTER"

PIC.2. - OSPI Register configuration to read volatile configuration register - command 0x85h.

Example 2.  "4 Byte Octal output fast read"  in Octal SPI Mode
In the PIC.3 you can find the OSPI Register configuration accordingly to the list above to "4 Byte Octal output fast read".

PIC.3 - OSPI Register configuration to read data - command 0x7Ch.

Additional infos:
- Flash is put to 4 Byte address mode.
- Flash mode is set to Octal without DQS.

Enabling /Disabling OSPI_CONFIG_REG.ENABLE_DTR_PRO  was tried additionally.
Enabling /Disabling OSPI_DEV_INSTR_RD_CONFIG_REG.DDR_EN_FLD was tried additionally.
From the the table "Table 12-5620. READ and WRITE Instruction Configuration" see PIC.4  the two last combinations were tested but, it they did not work to read.

PIC.4 - Table 12-5620. READ and WRITE Instruction Configuration

Tests are executed in Jacinto7 DRA821 Evaluation Module (EVM) User's Guide with flash memory Micron XccelaTm MT35XU512ABA

Could you please check what can be the issue?
Why is not OCTAL mode working for us, even though we are setting everything accordingly to read the memory data or read the registers.
If additional information are needed or a debugging session is required feel free to let us know.


Best Regards,
Egzon Mulaj

  • Hello once again,

    An example below :
    1.  Flash starts in Extended Spi mode (1 Lane).
    2.  Reading volatile configuration register (address  0 I/O mode) in EXTENDED SPI MODE (1 Lane) returns 0xFFh (Extended SPI - Default value).
    3.  Enabling writing via STIG  in Extended Spi mode (1 Lane)
    4.  Writing to volatile configuration register (address  0 I/O mode) in EXTENDED SPI MODE (1 Lane) value 0xC7h.
    5.  Disabling writing via STIG  in Extended Spi mode (1 Lane)  (Stuck in an infinite loop) OSPI_FLASH_COMMAND_CTRL_MEM_REG.MEM_BANK_REQ_IN_PROGRESS_FLD bit is never set back to 0.

    This raises few questions:
    - How shall we disable the writing after the mode is changed to OCTAL DDR mode if we are using STIG to send CMDs only?
    - Can we use STIG when the flash is set to Octal DDR without DQS mode?
    - If we want to change the number of lanes to bigger than 1 is STIG still useful or not?

    Thank you in advance.

    Best Regards,
    Egzon Mulaj

  • Hi Egzon,

    Closing this one as this has been discussed over calls and other threads.

    Regards,
    Parth