This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRA821U: About RTI Registers

Part Number: DRA821U

I checked "12.6.2 Windowed Watchdog Timer (WWDT)" of TRM (Rev.A) and found some unclear points, so please answer the following unclear points.

1.
Does the read/write mode (User and privilege mode) in the description of the RTI_DWDCTRL Register indicate the "Arm Architecture" processor mode?

2.
The description of RTI_WDSTATUS[5]DWWD_ST in TRM states the following, but if the wrong key is written, RTI_WDSTATUS[2]KEYST will be "1" but RTI_WDSTATUS[5]DWWD_ST will remain "0" becomes.
"This bit denotes whether the timewindow defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog."
Is this TRM description correct?