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Hii,
I am trying ddr diag test code which is available in PDK starterware, with that i am able to do write and read only 64KB, in my board i have 1GB of DDR memory, My ddr startaddress is 0x80000000. How can i do write and read completely. please help me on these.
Hello veerendra perugu
Thank you for the query.
Please expect delay in response due to the yearend holidays.
Is this a custom board? Please refer below thread on the ddr configuration
(+) AM3352: 3352 Power System Design - Processors forum - Processors - TI E2E support forums
Regards,
Sreenivasa
I am using Beagle bone black, which has 512MB of DDR, I am trying to do write and read, but it is allowing only 64KB after that I am getting crash. I need to do write and read completely, is there any configuration i need to change in order to access complete DDR 512MB. Even i tried my customized board which has 1GB of DDR it is also giving same problem.
Thanks
Veerendra
Hello veerendra perugu
Thank you for the inputs.
I have reassigned the query to the expert. Please expect delay in response due to the yearend holidays.
Regards,
Sreenivasa
/**
* \file ddr_diag_app_main.c
*
* \brief Example application main source file, which does DDR
* diagnostics.
*
* \detail Application demonstrates the diagnostics for DDR by
* writing and reading the bit patterns to the DDR.
*
*/
/*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
#include "types.h"
#include "error.h"
#include "board.h"
#include "soc.h"
#include "device.h"
#include "chipdb.h"
#include "cache.h"
#include "example_utils_mmu.h"
#include "console_utils.h"
#include "dma_utils.h"
/* Application header files */
#include "ddr_diag_app.h"
/* ========================================================================== */
/* Macros */
/* ========================================================================== */
/* None */
/* ========================================================================== */
/* Structures and Enums */
/* ========================================================================== */
/* None */
/* ========================================================================== */
/* Internal Function Declarations */
/* ========================================================================== */
/**
* \brief This API gets DDR size of the Board depending on Board ID
*
* \param ddrDiagAppBoardId board ID.
*/
static void DdrDiagAppGetMemSize (boardId_t ddrDiagAppBoardId);
/**
* \brief API for Diagnosing Address line failures.
*
* \param startAddr start address of DDR Memory for testing.
* \param size total size of Memory being tested.
*/
static void DdrDiagAppAddrTest(uint32_t startAddr, uint32_t size);
/**
* \brief API for diagnosing Data line failures.
*
* \param startAddr start address of DDR Memory for testing.
* \param size total size of Memory being tested.
*/
static void DdrDiagAppDataTest(uint32_t startAddr, uint32_t size);
/**
* \brief API for getting total memory to be tested.
*
* \retval size total size of Memory being tested.
*/
static uint32_t DdrDiagAppTestSize(void);
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/** \brief Data patterns to be written to DDR */
static const uint32_t gDdrDiagAppPattern[25U] =
{
0x55555555U, 0xaaaaaaaaU, 0x33333333U, 0xccccccccU,
0x0f0f0f0fU, 0xf0f0f0f0U, 0x00ff00ffU, 0xff00ff00U,
0x0000ffffU, 0xffff0000U, 0x00000000U, 0xffffffffU,
0x00000000U, 0x55555555U, 0xaaaaaaaaU, 0x33333333U,
0xccccccccU, 0x0f0f0f0fU, 0xf0f0f0f0U, 0x00ff00ffU,
0xff00ff00U, 0x0000ffffU, 0xffff0000U, 0x00000000U,
0xffffffffU,
};
/** \brief DDR Memory size */
static uint32_t gDdrDiagAppMemSize;
/** \brief Variable for Number of patterns to be tested */
static int32_t gDDrDiagAppMultiPattern = FALSE;
/** \brief Success/Failure status of tests */
static int32_t gFail = FALSE;
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
int main(void)
{
int32_t status = S_PASS;
uint32_t testAddr;
uint32_t testSize;
boardId_t ddrDiagAppBoardId;
/* Enable cache memory and MMU */
MMUConfigAndEnable();
CACHEEnable(CACHE_IDCACHE, CACHE_INNER_OUTER);
status = BOARDInit(NULL);
/* Initialize the UART console */
CONSOLEUtilsInit();
/* Select the console type based on compile time check */
CONSOLEUtilsSetType(CONSOLE_UTILS_TYPE_UART);
CONSOLEUtilsPrintf("BOARDInit status [0x%x]\n", status);
/* Print SoC & Board Information. */
SOCPrintInfo();
BOARDPrintInfo();
CONSOLEUtilsPrintf("\n***************************\n");
CONSOLEUtilsPrintf( "* Memory Test *\n");
CONSOLEUtilsPrintf( "***************************\n");
/* Get board Id to find the Size of DDR */
ddrDiagAppBoardId = BOARDGetId();
/* Get the size of DDR */
DdrDiagAppGetMemSize(ddrDiagAppBoardId);
/* Test */
CONSOLEUtilsPrintf("Test\t\t\tStatus\t Info\n");
CONSOLEUtilsPrintf("----------------\t------ --------------------\n");
/* Test size */
testSize = DdrDiagAppTestSize();
if(testSize != 0U)
{
testSize -= 0x100000U;
testAddr = START_ADDR_DDR + 0x100000U;
DdrDiagAppAddrTest(testAddr, testSize);
DdrDiagAppDataTest(testAddr, testSize);
}
CACHEDisable(CACHE_DCACHE, CACHE_INNER);
CONSOLEUtilsPrintf("\n Exiting\n");
return (gFail);
}
/* -------------------------------------------------------------------------- */
/* Internal Function Definitions */
/* -------------------------------------------------------------------------- */
static void DdrDiagAppGetMemSize (boardId_t ddrDiagAppBoardId)
{
/** TBD: Detect the size based on the Board ID.
* If the memory size is greter than 128MB update the
* Number of sections of DDR Memory in MMU utils to
* the appropriate value to eliminate aborts
*/
gDdrDiagAppMemSize = 128*1024*1024U;
}
static void DdrDiagAppAddrTest(uint32_t startAddr, uint32_t size)
{
uint32_t *addr = (uint32_t *)(startAddr);
uint32_t data=(startAddr);
uint32_t expectedData;
uint32_t index1;
uint32_t fAddrFail=FALSE;
char symbol = '|';
/* write memory */
CONSOLEUtilsPrintf("Address Test\t\tWrite\t\t%c", symbol);
for(index1 = 0U; index1 < size; index1 += 4U)
{
*addr = data;
addr++;
data += 4U;
if((index1 % 0x1000000U) == 0U)
{
switch(symbol)
{
case '|':
{
symbol = '/';
break;
}
case '/':
{
symbol = '-';
break;
}
case '-':
{
symbol = '\\';
break;
}
case '\\':
{
symbol = '|';
break;
}
default:
{
break;
}
}
CONSOLEUtilsPrintf("\rAddress Test\t\tWrite\t\t%c", symbol);
}
}
CACHEDataCleanInvRange((uint32_t *)startAddr, size);
/* verify */
CONSOLEUtilsPrintf("\rAddress Test\t\tRead \t\t%c", symbol);
addr = (uint32_t *)(startAddr);
for(index1 = 0U; index1 < size; index1 += 4U)
{
data = *addr;
expectedData = (uint32_t)addr;
if((index1 % 0x1000000U) == 0U && (fAddrFail != FALSE))
{
switch(symbol)
{
case '|':
{
symbol = '/';
break;
}
case '/':
{
symbol = '-';
break;
}
case '-':
{
symbol = '\\';
break;
}
case '\\':
{
symbol = '|';
break;
}
default:
{
break;
}
}
CONSOLEUtilsPrintf("\rAddress Test\t\tRead \t\t%c", symbol);
}
if(data != expectedData)
{
if(fAddrFail != FALSE)
{
CONSOLEUtilsPrintf("\rAddress Test\t\tFAIL\t\n");
fAddrFail = TRUE;
}
CONSOLEUtilsPrintf(
"\tFailure at 0x%08x: Expected=0x%08x Actual=0x%08x\n"
, addr, expectedData, data);
gFail = TRUE;
}
addr++;
}
if(!fAddrFail)
CONSOLEUtilsPrintf("\rAddress Test\t\t PASS \n");
}
static void DdrDiagAppDataTest(uint32_t startAddr, uint32_t size)
{
uint32_t *addr=(uint32_t *)(startAddr);
uint32_t data;
uint32_t expectedData;
uint32_t index1;
uint32_t index2;
uint32_t index3;
uint32_t offset = 0U;
uint32_t offsetMax = 0U;
uint32_t fDataFail = FALSE;
char symbol = '|';
if(gDDrDiagAppMultiPattern != FALSE)
{
offsetMax = 12U;
}
for(offset = 0U; offset <= offsetMax; offset++)
{
fDataFail = FALSE;
CONSOLEUtilsPrintf("Data Test %02d\t\tWrite\t\t%c", offset, symbol);
if(gDDrDiagAppMultiPattern != FALSE)
{
addr=(uint32_t *)(startAddr);
}
/* write patterns */
index2 = 0U;
for(index1 = 0U; index1 < size;index1 += 4U)
{
data = gDdrDiagAppPattern[(index2 + offset) % 13U];
*addr = data;
addr++;
index2++;
if((index1 % 0x1000000U) == 0U)
{
switch(symbol)
{
case '|':
{
symbol='/';
break;
}
case '/':
{
symbol='-';
break;
}
case '-':
{
symbol='\\';
break;
}
case '\\':
{
symbol='|';
break;
}
default:
{
break;
}
}
CONSOLEUtilsPrintf("\rData Test %02d\t\tWrite\t\t%c", offset, symbol);
}
}
CACHEDataCleanInvRange((uint32_t *)startAddr, size);
/* verify */
for(index3 = 0U; index3 < 1U; index3++)
{
CONSOLEUtilsPrintf("\rData Test %02d\t\tRead \t\t%c", index3, symbol);
addr = (uint32_t *)(startAddr);
index2 = 0U;
for(index1 = 0U; index1 < size; index1 += 4U)
{
data = *addr;
expectedData = gDdrDiagAppPattern[(index2 + offset)% 13U];
if((index1 % 0x1000000U) == 0U && (fDataFail != FALSE))
{
switch(symbol)
{
case '|':
{
symbol = '/';
break;
}
case '/':
{
symbol = '-';
break;
}
case '-':
{
symbol = '\\';
break;
}
case '\\':
{
symbol = '|';
break;
}
default:
{
break;
}
}
CONSOLEUtilsPrintf("\rData Test %02d\t\tRead \t\t%c", index3, symbol);
}
if(data != expectedData)
{
if(fDataFail != FALSE)
{
CONSOLEUtilsPrintf("\rData Test %02d\t\tFAIL \t\t\n", index3);
fDataFail = TRUE;
}
CONSOLEUtilsPrintf(
"\tFailure at 0x%08x: Expected=0x%08x Actual=0x%08x\n"
, addr, expectedData, data);
gFail = TRUE;
}
addr++;
index2++;
}
if(!fDataFail)
{
CONSOLEUtilsPrintf("\rData Test %02d\t\t PASS \n", index3);
}
}
}
}
static uint32_t DdrDiagAppTestSize(void)
{
uint32_t *addr = (uint32_t *)(START_ADDR_DDR);
uint32_t data = START_ADDR_DDR;
uint32_t expectedData;
uint32_t tempData;
uint32_t size = 0x20000U;
CONSOLEUtilsPrintf("Memory test size\t");
/* save data at START_ADDR_DDR in a variable */
tempData = *addr;
/* single write and read to start test and set expected data */
*addr = data;
CACHEDataCleanInvRange((uint32_t *)START_ADDR_DDR, 1U);
expectedData = *addr;
if(data != expectedData)
{
CONSOLEUtilsPrintf("FAIL\t Basic read/write test failed\n");
return 0U;
}
/* perform wrap test to detect size */
while(size < MAX_DDR_SIZE)
{
addr = (uint32_t *)(START_ADDR_DDR+size);
*addr = size;
CACHEDataCleanInvRange((uint32_t *)START_ADDR_DDR, 1U);
CACHEDataCleanInvRange((uint32_t *)addr, 1U);
data = *(uint32_t *)(START_ADDR_DDR);
if(data != expectedData)
break;
size *= 2U;
}
/* restore START_ADDR_DDR */
addr = (uint32_t *)(START_ADDR_DDR);
*addr = tempData;
CACHEDataCleanInvRange((uint32_t *)START_ADDR_DDR, 1U);
if(size != gDdrDiagAppMemSize)
{
CONSOLEUtilsPrintf("FAIL ");
gFail = TRUE;
}
else
{
CONSOLEUtilsPrintf(" PASS ");
}
if(size >= (1024U * 1024U * 1024U))
{
CONSOLEUtilsPrintf("Accessed memory size: %dGB\n",
size/(1024U * 1024U * 1024U));
}
else if(size >= (1024U * 1024U))
{
CONSOLEUtilsPrintf("Accessed memory size: %dMB\n", size/(1024U * 1024U));
}
else
{
CONSOLEUtilsPrintf("Accessed memory size: %dKB\n", size/(1024U));
}
return size;
}
this is the code i am using
Hii james,
I am checking memory browser in ccs. In that it is showing 0x80000000, these is the below log for 64kb write/read.
Board Init complete
ddr3_selftest entered...
cit MMUConfigAndEnable entered.........
cit MMUInit.11111.. entered.........
cit MMUInit..2222222222. entered.........
cit MMUInit..3333333333. entered.........
cit MMUInit..444444444444444. entered.........
cit MMUInit..5555555555555. entered.........
cit MMUInit..6666666666666. entered.........
cit mmuinit completed.........
cit base address completed.........
cit MMUMemRegionMap completed.........
cit MMUConfigAndEnable done...
cit CACHEEnable done...
cit BOARDInit status =0 done...
cit CONSOLEUtilsInit done...
BOARDInit status [0x0]
SoC : [AM335X]
Core : [A8]
entered into boardget id else part.........
soc family id........:2
board id get am335x.......
BoardGetIdAm335x............inside else part.
inside if statement..............
board_id at BOARDGetBoardName:6
id str table.......:
id str table.......:
id str table.......:
id str table.......:
id str table.......:
id str table.......:
id str table.......:
board id str.........:h
Board Detected : [BEAGLEBONEBLACK]
BoardGetBaseBoardRevNameAm335x.........11111111111111111........
BoardGetBaseBoardRevNameAm335x..........22222222222222222.................
board id get am335x.......
BoardGetIdAm335x............inside else part.
board rev.........inside if.
boardRev.....33333333333..........:0
pboardrev....4444444444444444444444...............:-2147239116
Base Board Revision : [UNKNOWN]
Daughter Card Revision: [UNKNOWN]
***************************
* Memory Test *
***************************
entered into boardget id else part.........
soc family id........:2
board id get am335x.......
BoardGetIdAm335x............inside else part.
DdrDiagAppGetMemSize........entered...............
Test Status Info
---------------- ------ --------------------
test size..............64kb.......
Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT..Address Test Write /
CIT..Address Test Write -
CIT..Address Test Write \
CIT..Address Test Write |
CIT......Address Test Read |
CIT......Address Test PASS
Data Test 00 Write |CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT.....Data Test 00 Write /
CIT.....Data Test 00 Write -
CIT.....Data Test 00 Write \
CIT.....Data Test 00 Write |
CIT....Data Test 00 Read |
CIT....Data Test 00 PASS
Exiting
UART Init complete
I2C Init complete
MCSPI Init complete
GPIO Init complete
======== Peripheral Initialization complete ========
Regards
Veerendra
Hii James,
The problem is if I keep testSize 64KB it if working fine, means test is passing. If I increase more than 64KB my test is not passing it is going to crash.
Write at 0x80109d14: Actual=0x0f0f0f0f
Write at 0x80109d18: Actual=0xf0f0f0f0
Write at 0x80109d1c: Actual=0x00ff00ff
Write at 0x80109d20: Actual=0xff00ff00
Write at 0x80109d24: Actual=0x0000ffff
Write at 0x80109d28: Actual=0xffff0000
Write at 0x80109d2c: Actual=0x00000000
write is not happening after 0x80109d2c this address. Help here if i need to change any registers.
Thanks
Veerendra
/**
* \file ddr_diag_app_main.c
*
* \brief Example application main source file, which does DDR
* diagnostics.
*
* \detail Application demonstrates the diagnostics for DDR by
* writing and reading the bit patterns to the DDR.
*
*/
/*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
#include "types.h"
#include "error.h"
#include "board.h"
#include "soc.h"
#include "device.h"
#include "chipdb.h"
#include "cache.h"
#include "example_utils_mmu.h"
#include "console_utils.h"
#include "dma_utils.h"
/* Application header files */
#include "app.h"
#include "ddr_diag_app.h"
/* ========================================================================== */
/* Macros */
/* ========================================================================== */
/* None */
/* ========================================================================== */
/* Structures and Enums */
/* ========================================================================== */
/* None */
/* ========================================================================== */
/* Internal Function Declarations */
/* ========================================================================== */
/**
* \brief This API gets DDR size of the Board depending on Board ID
*
* \param ddrDiagAppBoardId board ID.
*/
static void DdrDiagAppGetMemSize (boardId_t ddrDiagAppBoardId);
/**
* \brief API for Diagnosing Address line failures.
*
* \param startAddr start address of DDR Memory for testing.
* \param size total size of Memory being tested.
*/
static void DdrDiagAppAddrTest(uint32_t startAddr, uint32_t size);
/**
* \brief API for diagnosing Data line failures.
*
* \param startAddr start address of DDR Memory for testing.
* \param size total size of Memory being tested.
*/
static void DdrDiagAppDataTest(uint32_t startAddr, uint32_t size);
/**
* \brief API for getting total memory to be tested.
*
* \retval size total size of Memory being tested.
*/
static uint32_t DdrDiagAppTestSize(void);
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/** \brief Data patterns to be written to DDR */
static const uint32_t gDdrDiagAppPattern[25U] =
{
0x55555555U, 0xaaaaaaaaU, 0x33333333U, 0xccccccccU,
0x0f0f0f0fU, 0xf0f0f0f0U, 0x00ff00ffU, 0xff00ff00U,
0x0000ffffU, 0xffff0000U, 0x00000000U, 0xffffffffU,
0x00000000U, 0x55555555U, 0xaaaaaaaaU, 0x33333333U,
0xccccccccU, 0x0f0f0f0fU, 0xf0f0f0f0U, 0x00ff00ffU,
0xff00ff00U, 0x0000ffffU, 0xffff0000U, 0x00000000U,
0xffffffffU,
};
/** \brief DDR Memory size */
static uint32_t gDdrDiagAppMemSize;
/** \brief Variable for Number of patterns to be tested */
static int32_t gDDrDiagAppMultiPattern = FALSE;
/** \brief Success/Failure status of tests */
static int32_t gFail = FALSE;
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
int ddr3_self_test(void)
{
int32_t status = S_PASS;
uint32_t testAddr;
uint32_t testSize;
boardId_t ddrDiagAppBoardId;
// HW_WR_REG32((0x80000000 + 0x38), 0x000002A0);
// uint32_t regval = HW_RD_REG32(0x80000000 + 0x38);
// appPrint("ddr3_selftest entered...:%x\n", regval);
appPrint("ddr3_selftest entered...\n");
/* Enable cache memory and MMU */
MMUConfigAndEnable();
appPrint("cit MMUConfigAndEnable done...\n");
CACHEEnable(CACHE_IDCACHE, CACHE_INNER_OUTER);
appPrint("cit CACHEEnable done...\n");
status = BOARDInit(NULL);
appPrint("cit BOARDInit status =%d done...\n", status);
/* Initialize the UART console */
// CONSOLEUtilsInit();
appPrint("cit CONSOLEUtilsInit done...\n");
/* Select the console type based on compile time check */
// CONSOLEUtilsSetType(CONSOLE_UTILS_TYPE_UART);
// CONSOLEUtilsPrintf("BOARDInit status [0x%x]\n", status);
appPrint("BOARDInit status [0x%x]\n", status);
/* Print SoC & Board Information. */
SOCPrintInfo();
BOARDPrintInfo();
// CONSOLEUtilsPrintf("\n***************************\n");
// CONSOLEUtilsPrintf( "* Memory Test *\n");
// CONSOLEUtilsPrintf( "***************************\n");
appPrint("\n***************************\n");
appPrint( "* Memory Test *\n");
appPrint( "***************************\n");
/* Get board Id to find the Size of DDR */
ddrDiagAppBoardId = BOARDGetId();
/* Get the size of DDR */
DdrDiagAppGetMemSize(ddrDiagAppBoardId);
/* Test */
// CONSOLEUtilsPrintf("Test\t\t\tStatus\t Info\n");
// CONSOLEUtilsPrintf("----------------\t------ --------------------\n");
appPrint("Test\t\t\tStatus\t Info\n");
appPrint("----------------\t------ --------------------\n");
/* Test size */
// testSize = DdrDiagAppTestSize();
// testSize = 128*1024U;
testSize = 65536;
appPrint("test size...................:%d\n",testSize);
if(testSize != 0U)
{
// testSize -= 0x100000U;
testAddr = START_ADDR_DDR + 0x100000U;
// DdrDiagAppAddrTest(testAddr, testSize);
DdrDiagAppDataTest(testAddr, testSize);
}
CACHEDisable(CACHE_DCACHE, CACHE_INNER);
// CONSOLEUtilsPrintf("\n Exiting\n");
appPrint("\n Exiting\n");
return (gFail);
}
/* -------------------------------------------------------------------------- */
/* Internal Function Definitions */
/* -------------------------------------------------------------------------- */
static void DdrDiagAppGetMemSize (boardId_t ddrDiagAppBoardId)
{
/** TBD: Detect the size based on the Board ID.
* If the memory size is greter than 128MB update the
* Number of sections of DDR Memory in MMU utils to
* the appropriate value to eliminate aborts
*/
appPrint("DdrDiagAppGetMemSize........entered...............\n");
gDdrDiagAppMemSize = 64*1024U;//128 to 512
}
static void DdrDiagAppAddrTest(uint32_t startAddr, uint32_t size)
{
uint32_t *addr = (uint32_t *)(startAddr);
uint32_t data=(startAddr);
uint32_t expectedData;
uint32_t index1;
uint32_t fAddrFail=FALSE;
char symbol = '|';
/* write memory */
// CONSOLEUtilsPrintf("Address Test\t\tWrite\t\t%c", symbol);
appPrint("Address Test\t\tWrite\t\t%c\n", symbol);
for(index1 = 0U; index1 < size; index1 += 4U)
{
//appPrint("inside for loop......\n");
*addr = data;
addr++;
data += 4U;
// appPrint("addr:%x\n", addr);
if((index1 % 0x400U) == 0U)//0x1000000U//20000//0x100000U//10000//400
{
switch(symbol)
{
case '|':
{
symbol = '/';
//appPrint("inside switch...:/...\n");
break;
}
case '/':
{
symbol = '-';
//appPrint("inside switch...:-...\n");
break;
}
case '-':
{
symbol = '\\';
// appPrint("inside switch...:\\...\n");
break;
}
case '\\':
{
symbol = '|';
// appPrint("inside switch...:|...\n");
break;
}
default:
{
// appPrint("inside default break......\n");
break;
}
}
//CONSOLEUtilsPrintf("\rAddress Test\t\tWrite\t\t%c", symbol);
appPrint("CIT..Address Test\t\tWrite\t\t%c\n", symbol);
}
}
CACHEDataCleanInvRange((uint32_t *)startAddr, size);
/* verify */
// CONSOLEUtilsPrintf("\rAddress Test\t\tRead \t\t%c", symbol);
appPrint("CIT......Address Test\t\tRead \t\t%c\n", symbol);
addr = (uint32_t *)(startAddr);
for(index1 = 0U; index1 < size; index1 += 4U)
{
data = *addr;
expectedData = (uint32_t)addr;
if((index1 % 0x400U) == 0U && (fAddrFail != FALSE))//400//0x1000000U
{
switch(symbol)
{
case '|':
{
symbol = '/';
break;
}
case '/':
{
symbol = '-';
break;
}
case '-':
{
symbol = '\\';
break;
}
case '\\':
{
symbol = '|';
break;
}
default:
{
break;
}
}
//CONSOLEUtilsPrintf("\rAddress Test\t\tRead \t\t%c", symbol);
appPrint("CIT.......Address Test\t\tRead \t\t%c\n", symbol);
}
if(data != expectedData)
{
if(fAddrFail != FALSE)
{
// CONSOLEUtilsPrintf("\rAddress Test\t\tFAIL\t\n");
appPrint("\r.......Address Test\t\tFAIL\t\n");
fAddrFail = TRUE;
}
// CONSOLEUtilsPrintf(
// "\tFailure at 0x%08x: Expected=0x%08x Actual=0x%08x\n"
// , addr, expectedData, data);
appPrint(
"\tFailure at 0x%08x: Expected=0x%08x Actual=0x%08x\n"
, addr, expectedData, data);
gFail = TRUE;
}
addr++;
}
if(!fAddrFail)
//CONSOLEUtilsPrintf("\rAddress Test\t\t PASS \n");
appPrint("CIT......Address Test\t\t PASS \n");
}
static void DdrDiagAppDataTest(uint32_t startAddr, uint32_t size)
{
uint32_t *addr=(uint32_t *)(startAddr);
uint32_t data;
uint32_t expectedData;
uint32_t index1;
uint32_t index2;
uint32_t index3;
uint32_t offset = 0U;
uint32_t offsetMax = 0U;
uint32_t fDataFail = FALSE;
char symbol = '|';
if(gDDrDiagAppMultiPattern != FALSE)
{
offsetMax = 12U;
}
for(offset = 0U; offset <= offsetMax; offset++)
{
fDataFail = FALSE;
// CONSOLEUtilsPrintf("Data Test %02d\t\tWrite\t\t%c", offset, symbol);
appPrint("Data Test %02d\t\tWrite\t\t%c", offset, symbol);
if(gDDrDiagAppMultiPattern != FALSE)
{
addr=(uint32_t *)(startAddr);
}
/* write patterns */
index2 = 0U;
for(index1 = 0U; index1 < size;index1 += 4U)
{
data = gDdrDiagAppPattern[(index2 + offset) % 13U];
*addr = data;
addr++;
// appPrint("write address:%x\n", addr);
index2++;
if((index1 % 0x400U) == 0U)//0x1000000U
{
switch(symbol)
{
case '|':
{
symbol='/';
break;
}
case '/':
{
symbol='-';
break;
}
case '-':
{
symbol='\\';
break;
}
case '\\':
{
symbol='|';
break;
}
default:
{
break;
}
}
//CONSOLEUtilsPrintf("\rData Test %02d\t\tWrite\t\t%c", offset, symbol);
appPrint("CIT.....Data Test %02d\t\tWrite\t\t%c\n", offset, symbol);
}
}
CACHEDataCleanInvRange((uint32_t *)startAddr, size);
/* verify */
for(index3 = 0U; index3 < 1U; index3++)
{
//CONSOLEUtilsPrintf("\rData Test %02d\t\tRead \t\t%c", index3, symbol);
appPrint("CIT....Data Test %02d\t\tRead \t\t%c\n", index3, symbol);
addr = (uint32_t *)(startAddr);
index2 = 0U;
for(index1 = 0U; index1 < size; index1 += 4U)
{
data = *addr;
expectedData = gDdrDiagAppPattern[(index2 + offset)% 13U];
if((index1 % 0x400U) == 0U && (fDataFail != FALSE))//0x1000000U
{
switch(symbol)
{
case '|':
{
symbol = '/';
break;
}
case '/':
{
symbol = '-';
break;
}
case '-':
{
symbol = '\\';
break;
}
case '\\':
{
symbol = '|';
break;
}
default:
{
break;
}
}
//CONSOLEUtilsPrintf("\rData Test %02d\t\tRead \t\t%c", index3, symbol);
appPrint("CIT......Data Test %02d\t\tRead \t\t%c\n", index3, symbol);
}
if(data != expectedData)
{
if(fDataFail != FALSE)
{
//CONSOLEUtilsPrintf("\rData Test %02d\t\tFAIL \t\t\n", index3);
appPrint("\rData Test %02d\t\tFAIL \t\t\n", index3);
fDataFail = TRUE;
}
// CONSOLEUtilsPrintf(
// "\tFailure at 0x%08x: Expected=0x%08x Actual=0x%08x\n"
// , addr, expectedData, data);
appPrint(
"\tFailure at 0x%08x: Expected=0x%08x Actual=0x%08x\n"
, addr, expectedData, data);
gFail = TRUE;
}
addr++;
index2++;
}
if(!fDataFail)
{
// CONSOLEUtilsPrintf("\rData Test %02d\t\t PASS \n", index3);
appPrint("CIT....Data Test %02d\t\t PASS \n", index3);
}
}
}
}
static uint32_t DdrDiagAppTestSize(void)
{
uint32_t *addr = (uint32_t *)(START_ADDR_DDR);
uint32_t data = START_ADDR_DDR;
uint32_t expectedData;
uint32_t tempData;
uint32_t size = 0x400U;//0x20000U;
// CONSOLEUtilsPrintf("Memory test size\t");
appPrint("Memory test size\t\n");
/* save data at START_ADDR_DDR in a variable */
tempData = *addr;
/* single write and read to start test and set expected data */
*addr = data;
appPrint("......DdrDiagAppTestSize.....111111111111111.......\n");
CACHEDataCleanInvRange((uint32_t *)START_ADDR_DDR, 1U);
appPrint("......DdrDiagAppTestSize.....222222222222222.......\n");
expectedData = *addr;
appPrint("......DdrDiagAppTestSize.....333333333333333.......\n");
appPrint(".............expected data:%d\n",expectedData);
if(data != expectedData)
{
//CONSOLEUtilsPrintf("FAIL\t Basic read/write test failed\n");
appPrint("FAIL\t Basic read/write test failed\n");
return 0U;
}
/* perform wrap test to detect size */
while(size < MAX_DDR_SIZE)
{
appPrint("......DdrDiagAppTestSize.....4444444444444.......\n");
addr = (uint32_t *)(START_ADDR_DDR+size);
*addr = size;
appPrint("above...........cached data clean in vrange..\n");
CACHEDataCleanInvRange((uint32_t *)START_ADDR_DDR, 1U);
appPrint("ddrdiagapptest....................4141414141414141414.............\n");
CACHEDataCleanInvRange((uint32_t *)addr, 1U);
appPrint("ddrdiagapptest....................44242424242424242424............\n");
data = *(uint32_t *)(START_ADDR_DDR);
appPrint("data in while loop:%d\n", data);
if(data != expectedData)
{
appPrint("not equal entered .....break........\n");
break;
}
size *= 2U;
}
appPrint("after while...................\n");
/* restore START_ADDR_DDR */
addr = (uint32_t *)(START_ADDR_DDR);
*addr = tempData;
appPrint("......DdrDiagAppTestSize.....555555555555555.......\n");
CACHEDataCleanInvRange((uint32_t *)START_ADDR_DDR, 1U);
appPrint("......DdrDiagAppTestSize.....666666666666666666.......\n");
if(size != gDdrDiagAppMemSize)
{
//CONSOLEUtilsPrintf("FAIL ");
appPrint("FAIL ");
gFail = TRUE;
}
else
{
// CONSOLEUtilsPrintf(" PASS ");
appPrint(" PASS ");
}
if(size >= (1024U * 1024U * 1024U))
{
// CONSOLEUtilsPrintf("Accessed memory size: %dGB\n",
// size/(1024U * 1024U * 1024U));
appPrint("Accessed memory size: %dGB\n",
size/(1024U * 1024U * 1024U));
}
else if(size >= (1024U * 1024U))
{
//CONSOLEUtilsPrintf("Accessed memory size: %dMB\n", size/(1024U * 1024U));
appPrint("Accessed memory size: %dMB\n", size/(1024U * 1024U));
}
else
{
// CONSOLEUtilsPrintf("Accessed memory size: %dKB\n", size/(1024U));
appPrint("Accessed memory size: %dKB\n", size/(1024U));
}
return size;
}
testSize = 65536;
Hii James,
The above code is the one i am using it is able to read 64KB only, If I try more than that it is crashing at
Write at 0x80109d2c: Actual=0x00000000 this address.
Thanks
Veerendra