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AM6422: mmc0 / mmc1 intermittent; how do I force slower bus (HS200->HS100) to test?

Part Number: AM6422

We've got a batch of 25 prototype boards using the AM6422 booting from SD card and/or eMMC chip via jumper configuration selection.  We're getting a lot of error -110 stuff similar to *many* other posts here on e2e.ti.com.

We want to slow the bus down from HS200 mode to HS100 mode.

How?

From one related question:

&mmc2 {
    /* SW5-3 in ON position */
    status = "okay";

    vmmc-supply = <&evm_3v3_sw>;
    bus-width = <8>;
    ti,non-removable;
    max-frequency = <192000000>;

    pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
    pinctrl-0 = <&mmc2_pins_default>;
    pinctrl-1 = <&mmc2_pins_hs>;
    pinctrl-2 = <&mmc2_pins_ddr_1_8v>;
    pinctrl-3 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_conf>;
};

mmc2_iodelay_hs200_1_8v_conf: mmc2_iodelay_hs200_1_8v_conf {
    pinctrl-single,pins = <
        0x194 (A_DELAY(285) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
        0x1AC (A_DELAY(189) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
        0x1B8 (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A21_OUT */
        0x1C4 (A_DELAY(0) | G_DELAY(70)) /* CFG_GPMC_A22_OUT */
        0x1D0 (A_DELAY(730) | G_DELAY(360)) /* CFG_GPMC_A23_OUT */
        0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
        0x1E8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
        0x1F4 (A_DELAY(70) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
        0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
        0x368 (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_CS1_OUT */
        0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
        0x1A8 (A_DELAY(231) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
        0x1B4 (A_DELAY(39) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
        0x1C0 (A_DELAY(91) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
        0x1D8 (A_DELAY(176) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
        0x1E4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
        0x1F0 (A_DELAY(101) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
        0x1FC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
        0x364 (A_DELAY(360) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
    >;
};

  When I set max-frequency less than 192000000,the probability of recurrence is reduced.,I don’t know how to slove the trouble. [emphasis mine]

This indicates it is possible, I just need to know how. 

Thanks!

  • We have confirmed that SD cards marked "A1" boot reliably with the default .dts file, and cards that are not marked, and have (empirically) significantly (1/3? 1/4?) lower IOPS, are marginal.

    We have also confirmed we can change the .dts to set the SD card bus to 100MHz and those non-A1 marginal cards do boot reliably.

    The eMMC chip we're using is slower still (it benchmarks at 320/73 read/write IOPS, and that's in HS200 mode). 

    Please advise, if at all possible, changes we can make to the .dts for the mmc config to get the eMMC booting reliably.  (We're seeking a higher performance chip for the next revision.)

  • Hi John,

    Removing "ti,otap-del-sel-hs200" and "ti,otap-del-sel-hs400" properties in k3-am64-main.dtsi should disable HS200 and HS400 support.

  • We have 2 out of 25 units that do not detect all of the eMMC unless we slow the mmc0 down to 25MHz, at which point all four partitions are correctly detected.  Once detected we can go to at least 50MHz and operation succeeds; perhaps even 100MHz -- but we expect compatibility at 200MHz, yes?

    We have 7 our of 25 units that often throw timeout errors (-110) when booting from SD or eMMC unless we slow to 100MHz, at which point they work fine.  "Often" because they work with some SD cards and not others, and even that is merely statistical.

  • I have found an A2 marked SD card also marked U3 and V30 that does not work; same/similar symptoms

  • Hi John,

    I am routing your query to our MMC hardware expert to comment on the hardware/board diagnosis first.

  • Which MMC port are you connecting each device?  MMC0 should only be used with an eMMC devices and MMC1 should only be used with SD Cards.

    We only support the speeds shown in the datasheet. See the MMCSD timing section of the datasheet.

    HS200 is a valid data transfer speed defined in the eMMC standard, but not HS100. So, it is not clear what you mean when referencing HS100.

    I suspect you have signal integrity issues based on your comments that indicate the interface is not working at much lower operating frequencies.

    You should use a very high-bandwidth scope and probes to examine signal quality of all signals as close as possible to both AM64x and attached memory device. While checking signal integrity, also verify there is plenty of timing margin for both the AM64x and memory device based on the requirements defined for your specific mode of operation.

    Regards,
    Paul