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TMS320C6657: Questions regarding Clocking

Darren (FAE)
Expert 5483 points

Part Number: TMS320C6657

I know the datasheet gives some input clock requirement parameters for CORECLK P/N. For reference:

Table 5-6. Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements

But I don't see the differential voltage swing requirements, etc.
Are these LVDS inputs? LJCB inputs? THat is what I understand from:

6.3 Power Supply to Peripheral I/O Mapping
CVDD -> LJCB -> CORECLK

If they are LJCB inputs, then the datasheet references this document:

https://www.ti.com/lit/an/sprabi2d/sprabi2d.pdf

3.4 Input Clock Termination Requirements (I don't see CORECLK listed here?)

7.4.4 LJCB Differential Clock Inputs

These sections indicate HCSL clock inputs are allowable with AC-coupling capacitors.
The LJCB inputs have internal biasing so no termination is needed on the DSP-side of the AC caps.

So, assuming AC-caps are needed and we don't need to worry about the exact bias voltages, then what is the required minimum / maximum differential voltage difference needed for the CLK signals?

  • 0
    TI__Expert 5483 points

    Just a quick follow-up to my above.

    In Table 5-6. Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements... 

    1) The Tr/Tf timing is defined with a differential ΔV change of 125mV or 250mV?

    2) That table lists required input duty cycle as 45%~55% - is this the differential duty cycle, or the single-ended duty cycle requirement? (there could be some skew between P/N)

    3) There is a parameter "tj" which defines period jitter (pk-pk), right...? Does it mean both OUTP/N need to be within 100ps MAX or is it the differential jitter?

    Regards,
    Darren

  • 0 in reply to Darren (FAE)
    TI__Expert 5483 points

    Hi Team,

    I found out the datasheet actually has most of what I need.
    (AC characteristics like jitter, Tr/Tf, etc are in Table 5-6, while the required voltage levels are in Figure 5-6)

    One point I didn't understand.
    What is the frequency tolerance?

    Say we have 100MHz (10ns cycle time) differential input.
    As long as the cycle time limits are met (3.2ns ~ 25ns) does it matter, since the PLL is generating the actual clock anyway?
    Or is there some ±ppm frequency limit that needs to be met?

    Regards,
    Darren