• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 100 subscribers
  • Views 274 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6746: McBSP input using EDMA3 generates bus errors

Jiahui Gao
Genius 10745 points

Part Number: TMS320C6746

Hi team，

Customer has some questions

I am using McBSP I2S receive with frame sync, clock and data all generated externally (2 channels, 48kHz). The command file sets all memory to L2 RAM. EDMA3 is set up to repeatedly transfer 16 32-bit sample pairs to a buffer in L2 RAM. However, all McBSP EDMA3 events result in TCC bus errors. Zip file DMA_Test.zip contains exported project, including screenshots. Screenshot_1 shows PaRAM initialization. Screenshot_2 shows the result of a breakpoint in the EDMA event handler. Note that the returned interrupt status code is 4 - shouldn't this be the TCC code instead? Only one event handler interrupt is ever generated. Screenshot_3 shows the result of a breakpoint in the TC0 error handler - note that the error details register value is 0. I have extensively reviewed the McBSP and EDMA3 chapters in the Technical Reference Manual, and cannot see the source of the problem. Please advise.

DMA_Test.zip

Could you help?

Thanks & Regards,

Jiahui