Hello,
Reading through the reference manual , the AM6412 supports interfacing to an FPGA through the GPMC.
For our design the GPMC will be used for the following 2 operations :
1)
First will be the Parallel programming of the FPGA
The FPGA has various modes of programming. One preferred method is the parallel bus programming.
This FPGA requires the following :
- GPMC clock should run continuously while configuring the FPGA device
- Monitoring of a READY signal (this is an FPGA output , to inform the CPU that it can receive data)
- Control of a VALID signal (CPU out signal)
The host must drive no more than six data words after the deassertion of the READY signal
The host must synchronize the READY signal to the CLK signal using a 2-stage register synchronizer.
2)
Register access (AM6412 will read - write FPGA registers).
The FPGA to be used , requires a parallel bus for register access , of 12 address bits and 16 bit data bus.
From the FPGA side this interface is similar to an ASRAM interface (custom built interface).
Can the GPMC support the above 2 operations ? I understand that the 2nd operation (register access) is a custom built design so further information is required. Nevertheless this is based on a standard ASRAM 16 bit interface.
Thanks
Alex
