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TDA4VM: Recommendation for SAMPLEDELAY to charge the AFE capacitance during the acquisition period

Part Number: TDA4VM

Hi Kevin,

In the referenced E2E post https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1096609/tda4vm-what-s-the-input-impedance-of-adc-port-of-tda4vmyou state the following:

But here is the key point: the 1K resistance and the 5.5pF (+ parasitic capacitances) creates an RC time constant of 5.5ns. You always need 9 or 10 time constants to charge to a 12-bit accuracy level.

Is this relationship between RC time constant and the time it takes to charge to a particular accuracy level (9-10 time constants for 12 bit accuracy) specific to the TI ADC design or is this ADC design in general? Can you point me to any further collateral on this relationship?

Thanks,

Jelena