• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 97 subscribers
  • Views 395 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Could the ARM-side EDMA3 driver prevent QDMA transfers on the DSP?

Lee Holeva
Genius 4615 points

I've still not been able to resolve the following problem:

1.  I built the EDMA3 LLD sample code for the DSP and got this to work on the DSP, by-itself with the ARM halted.

2.  I then copied and pasted much of the qdma_test sample code into my own code that attempts to do QDMA while the ARM is running.  What happens is that the ARM sets up the DSP and sends the source address for the QDMA transfer to the DSP via MessageQ.  The data source is in shared memory and the destination is in L1D.  This part works fine.  I then setup the QDMA transfers, I can see the source address, destination address, and the acnt, bcnt, and cnt values in the PaRAM memory, I give EDMA3 on the DSP the trigger word, I get a successful completion interrupt, yet no transfers actually happen.  Why am I not seeing transfers?  Could the EDMA3 Low Level Driver in Linux somehow be preventing the transfers?

 

Lee Holeva

 

  • 0
    Genius 4615 points

    I added some code to look at the Channel Control Registers.  I see QDMA channel 7 getting enabled, but nothing else.  Does this make sense?

    CC registers:

    Values before the trigger:

     

    Values after the trigger:

     

    In PaRAM memory both the source and destination addresses are getting set.

    Update:

    I rewrote the code to do DMA with a manual trigger and got the same result, a successful completion interrupt, the PaRAM values got reset to zero, but no actual transfer of data.  I also looked at the EMR and SER registers, both before and after the transfer, and they both remained zero.  Apparently, despite having acnt, bcnt, and ccnt non-zero, the EDMA controller thinks that it is doing a dummy transfer.

    Update Secunda:

    I tried to program the EDMA directly, copying code from:

    http://processors.wiki.ti.com/index.php/Programming_EDMA_without_EDMA3LLD_package

    I changed the addresses, but I still do not get any transfers.  acnt goes to zero as it should.

     

    Lee Holeva

     

  • 0 in reply to Lee Holeva
    Genius 4615 points

    I've narrowed-down the problem.  If I change the destination address to be in DDR memory, the DMA transfers work.  I also redid the EDMA3 example making the destination in L1D memory and it too failed.  So there appears to be an issue performing DDR to L1D DMA transfers by the DSP.  I have the same problem with L2 memory, IRAM.  Any idea of how to fix this?

    Update:

    DMA from DDR to L1D is now working. The fix is to add 0x30000000 to the L1D buffer address.  This has been a rather frustrating experience. For EDMA3 on the DSP, I have been referring to the following documents:

    C6748 EDMA3 Controller User's Guide

    C6748 DSP System Reference Guide

    C674x DSP Megamodule Reference Guide

    Ti81xx-PSP EDMA Driver user Guide

    EDMA3 Driver User's Guide and html docs

    various wiki pages

    As far as I can tell, the required address translation for L1D is not mentioned anywhere in the above.  Both the DDR2 and the DDR3 EVMs require the same fix.  Where is this documented?

    Update Secunda:

    The documentation is in the data sheet under L3 memory map:

    http://focus.ti.com/lit/ds/symlink/tms320c6a8168.pdf

    This really needs to be put with the EZSDK (PSP?) and/or the EDMA3 documentation.

    L:ee Holeva

     

     

     

  • 0 in reply to Lee Holeva
    Expert 2030 points

    I am having the same problem. Please see this post. Offsetting L2 address by 0x3000 0000 does not do the trick for me.

     

    RV

     

  • 0 in reply to RV
    Genius 4615 points

    RV said:

    I am having the same problem. Please see this post. Offsetting L2 address by 0x3000 0000 does not do the trick for me.

    Did you try using just EDMA3?  Programming the EDMA3 Low Level Driver directly, with the offset for L1D, did the trick for me.

    Lee Holeva

     

  • 0 in reply to RV
    Genius 4615 points

    RV said:

    I am having the same problem. Please see this post. Offsetting L2 address by 0x3000 0000 does not do the trick for me.

    Did you try using just EDMA3?  Programming the EDMA3 Low Level Driver directly, with the offset for L1D, did the trick for me.

    Lee Holeva

     

  • 0 in reply to Lee Holeva
    Expert 2030 points

    I would appreciate pointers as to  where to find the source file to modify in the EZSDK and which function to modify.

    Sample code would be a huge bonus !!

    Regards

    RV