Hi Team,
We are using AM5706BCBDJA in our project.
2 spi devices are connected to single SPI core
chip select 0 is connected to device A
chip select 1 is connected to device B
While asserting CS0, CS1 also gets asserted. CS0 is getting deasserted after SPI cycle but CS1 is low until power cycle and vice versa. Please help us with this issue.