• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 97 subscribers
  • Views 261 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Questions on power management on DM6437

Anonymous
Anonymous
Other Parts Discussed in Thread: TMS320DM6437

Hi,

 

I would like to ask some questions on power management.

 

From section 3.2 Power Considerations of sprs345d TMS320DM6437 Digital Media Processor & section 6.7 6.7 PSC Registers and chapter 7 Power Management of SPRU978E TMS320DM643x DMP DSP Subsystem Reference Guide, there exist the following modes for power consumption on DM6437 device:

 

Clock gating

Frequency scaling

PLL bypass & power down

Sleep mode

3.3V I/O power down

Video DAC Power Down

 

Question 1:

1.    In the extreme, how much (in percentage) power consumption can be achieved if one aggressively applies all these methods? Could TI provide any statistics?

2.    In normal case, how much percentage of power can be saved?

 

 

 

On page 75 of SPRU978E, TMS320DM643x DMP DSP Subsystem:

 

 

Question 2

 

What does the values of NEXT mean here? Does “2h Disable state” correspond to “clock gating” or “power down”, or else? What does

1.    SwRstDisable

2.    SyncReset

mean, respectively?

 

 

 

Zheng

  • 0
    TI__Genius 15310 points

    Zheng,

    For Question 1, can you point them to the power spreadsheet?  Mr. Zhao can get answers to all his queries through the spreadsheet.  The only exception may be the 3.3V I/O power down; I am not sure what that refers to.

    For Question 2, each state is clearly defined in SPRU978.

     

     


  • Anonymous
    0 Anonymous in reply to Viet Dinh

    Viet,

     

     

    Question 1: Thanks you for referring me to the spreadsheet. I am experimenting different specifications with it now.

     

    Question 2:

    1.    Does “module clock off” mean clock gating?

    2.    What is “full static CMOS”?

    3.    For SyncReset and SwRstDisable, both description says that they are “not expected to be initiated by software”. Their common characteristic is with module reset asserted, so do they exist only when user pressing a reset button, or during the short interval before or after booting?

     

     

     

    Zheng