AM625: Ethernet MDIO clock is 700K and it's not changing while updating the clock divider register

hello,

We are using Eth driver of "SDKRA v08.04.00.21"

We configured the MDC clock to 2.5 Mhz which is a standard value. but when we measured it we found the MDC = 700 KHZ. we tried to change the clock divider "CLKDIV" of  Reg CONTROL_REG but the clock doesn't change .

- how to configure the clock to 2.5 Mhz and what is the value of the input clock to the CPSW ?

* the CPPI_CLK is hardcoded in the driver to 320MHZ how it's calculated *