AM625: WKUP domain clock output - dts support

Jhon Q said:

We need to get 32.768Khz clock on pad A12 (WKUP_CLKOUT0) by default is it configured to supply 25Mhz. We need to change register 0x43008020 to value 0x5. Is it possible to configure this bit via dts file?

This is fundamentally possible by setting this up as a dedicated clock with the correct TISCI clock references using the assigned-clocks and assigned-clock-parents properties and the proper clock IDs from the AM62x TISCI documentation (https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html) however the challenge is that Linux will not activate/disable any clock that itself is not referenced from anywhere else. While it is possible to change this behavior by adding clk_ignore_unused to the Kernel command line (I found this option discussed here), doing so may have other system-wide implication, and forcing a certain Kernel command like just doesn't seem very clean to me,

Another way to workaround this and changing the clock signal sourcing the WKUP_CLKOUT0 pin by only using device tree is piggy-backing on an existing devices and adding those additional assigned-clocks and assigned-clock-parents properties there, so that clock will be brought up together with that device. Below example shows how to do that in U-Boot, and the resulting control register change you wanted. It should work in a similar manner in Linux but such low-level setup is typically left to the bootloader.

$ git show
commit abb607be1cf87702ba2cb6a79ab93dbb7142c195 (HEAD -> ti-u-boot-2021.01-wkup-clkout0-dev)
Author: Andreas Dannenberg <dannenberg@ti.com>
Date:   Mon Jan 23 15:13:17 2023 -0600

    arm: dts: k3-am625-sk: Output 32K RC clock through WKUP_CLKOUT0

    Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>

diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts
index bfe1e78ed8..29f054ffed 100644
--- a/arch/arm/dts/k3-am625-sk.dts
+++ b/arch/arm/dts/k3-am625-sk.dts
@@ -14,6 +14,19 @@
        model = "Texas Instruments AM625 SK";
 };

+&main_uart0 {
+               /*
+                * CLK_32K_RC_SEL_OUT0 -> WKUP_CLKOUT0_IN
+                *
+                * Note that we hijack the main_uart0 node for this as we know
+                * it is always being brought up, and it doesn't require any
+                * assigned-* properties, so there is no danger of overwriting
+                * existing SoC-level definitions with our "extra" assignments.
+                */
+               assigned-clocks = <&k3_clks 157 158>;
+               assigned-clock-parents = <&k3_clks 157 164>;
+};
+
 &cpsw_port2 {
        phy-mode = "rgmii-rxid";
        phy-handle = <&cpsw3g_phy1>;

Here you can see how the mux setting was set to 5 (Note the value '5' you requested means the 32kHz RC clock is used, and NOT the 32.768kHz crystal oscillator called LFOSC0)

=> md 0x43008020 1
43008020: 00000005                               ....

If it was me I'd probably do that setup in a U-Boot boardfile instead, calling the clock APIs.

Regards, Andreas