TDA4VM: DSP C6x_1 UDMA VINTR alloc failed

hongyao.jin

Part Number: TDA4VM
Other Parts Discussed in Thread: SYSCONFIG

TDA4VM

SDK 07_03_00_07

DSP C6x_1

1. i use appUdmaCopyNDGetHandle() function to get dma channel , but I find that when i call more than 8 times, an error (VINTR alloc failed )has occurred. as the image show.

and i find it because rmInitPrms->numVintr is 8, so I can't call it more than 8 times. as image show .

2. I would like to know if I can configure this (rmInitPrms->numVintr) and how

over 2 years ago

0 Brijesh Jadav over 2 years ago

TI__Guru**** 477555 points

Hi,

You could allocate more interrupts in the resource manager. But why do you require more than 8 interrupts on C6x? Can you please try using shared interrupts, instead of exclusive interrupts?

You could use shared event and then can use master Event handler as shown below.

cqEventPrms.eventMode = UDMA_EVENT_MODE_SHARED;
cqEventPrms.masterEventHandle = Udma_eventGetGlobalHandle(drvHandle);

Regards,

Brijesh

0 Sikai Lu over 2 years ago in reply to Brijesh Jadav

TI__Expert 3241 points

Dear Brijesh,

I think there might be some misunderstanding here. Customer now has used 8 channels of UDMA on C6x and now they want 1-2 channels more.

Hope to check with you that do you have a hardware limitation on C6X of UDMA channels? Otherwise how could we add more channels? Thanks.

Sikai

0 Brijesh Jadav over 2 years ago in reply to Sikai Lu

TI__Guru**** 477555 points

Hi Sikai Lu,

We can definitely add more UDMA channels for C6x. This should be done in the resource manager. Please refer to below faq for adding more channels in resource manager using sysconfig tool.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1097038/faq-tda4vm-workflow-and-resource-allocation-build-flow-for-sysconfig-tool

Regards,

Brijesh

0 Sikai Lu over 2 years ago in reply to Brijesh Jadav

TI__Expert 3241 points

Dear Brijesh,

Thanks for your guide , here is our change result:

It reports "exceed" error, is it caused by mis-operation?

Sikai

0 Brijesh Jadav over 2 years ago in reply to Sikai Lu

TI__Guru**** 477555 points

Hi Sikai,

All resource are fully allocated by default. So if you need any additional resource, you need to first reduce them from other core and then can allocate in this core. Lets say if you require UDMA RX channels on C6x, you need to reduce them from another core and then can allocate them on C6x core.. This error will then go away.

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

1. i modefi sciclient_defaultBoardcfg_rm.c and compile error

2. Can I do this in the psdkqa directory because I don't have a PSDKRA directory

0 Sikai Lu over 2 years ago in reply to Brijesh Jadav

TI__Expert 3241 points

Dear Brijesh,

Thanks. However customer now are using QNX system so they do not have PDKRA/ path.

From my point of view, since we just modify the RM related configuration so only MCU1_0 code has been changed and in this case even they use PDKQA/ the changes should be the same right?

Sikai

0 Brijesh Jadav over 2 years ago in reply to Sikai Lu

TI__Guru**** 477555 points

Hi Sikai,

But which component is loading QNX on A72? Is it SBL or uboot? If it is SBL, please update the sciclient_boardcfg_rm.c file in the PSDKRA/pdk, rebuild boardcfg and then SBL and then try loading QNX. If it is SPL/uboot, please generate rm_cfg.c file, update it in k3-image-gen-2022.01/soc/j721e/evm/ folder, rebuild uboot and sysfw.itb and then use updated uboot to load QNX.

I see customer is updating it in the PDK, which is part of psdkqa. This is not correct place. Depending on which component is loading QNX, please update the appropriate component..

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

hi , i do not find the PSDKLA/board_support directory

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Hi,

Which SDK release are you using? It seems you are using yocto to build Linux kernel? can you please confirm?

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

1. SDK is 07_03_00_07

2. i want use yocto to build uboot.img

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Karthik Ramanan, can you please help on updating rm_cfg.c file when building uboot using yocto?

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

that is what i want to do , but i do not find rm_cfg.c

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Hi,

Give me sometime, i will get back to you today.

Regards,

Brijesh

0 Karthik Ramanan over 2 years ago in reply to Brijesh Jadav

TI__Guru** 113810 points

Hi,

Customers don't use the Yocto flow for generating artifacts for the QNX based system.

However, you can use the following method if you still want to insert this into the Yocto flow.

Using the k3-image-gen, you can generate your own version of the sysfw.itb.
This sysfw.itb can be replaced in the Yocto build, the relevant recipes that you need are called out here:
- meta-ti/recipes-bsp/ti-linux-fw/ti-linux-fw.inc
- meta-ti/recipes-bsp/ti-sci-fw/ti-sci-fw_git.bb

Hope this helps.

Regards
Karthik

0 hongyao.jin over 2 years ago in reply to Karthik Ramanan

Expert 1220 points

1. we use SBL boot mode， and HLOS_BOOT = development

2. now , we update sciclient_defaultBoardcfg_rm.c in PSDKQA\PDK\packages\ti\drv\sciclient\soc\V1 folder and step c complete success.

but there are some questions about step d, I need to compile SBL, but what image do I need to rebuild to generate in SBL, is it tiboot3, u-boot.img, or tifs.bin

0 Sikai Lu over 2 years ago in reply to hongyao.jin

TI__Expert 3241 points

You only need to rebuild SBL and rename it as tiboot3.

Since you are using SBL and boot from EMMC please refer to this graph:

This tiboot3 is different from what you built from Linux SDK.

Sikai

0 hongyao.jin over 2 years ago in reply to Sikai Lu

Expert 1220 points

1. i increase DSP C66_0 UDMA channel count to 14 in sysconfig , and get sciclient_defaultBoardcfg_rm.c

2. update sciclient_defaultBoardcfg_rm.c in PSDKQA\PDK\packages\ti\drv\sciclient\soc\V1 folder

make sciclient_boardcfg -sj4

make sciclient_boardcfg BUILD_HS=yes -sj4

3. rebuild tiboot3.bin and replace in emmc

but error (VINTR alloc failed ) still occurred

0 Sikai Lu over 2 years ago in reply to hongyao.jin

TI__Expert 3241 points

Dear Brijesh,

To check whether this is a compling issue we tried to decrease the channel to 6 rather than increasing.

Customer doubt that the problem may be caused by lack of interrupt instead of channels.

Dear Chuang,

1. Could you share the configuration of 6 channels and how you confirm that you have passed the compling?

2. Could you share the current error configuration?

Sikai

0 hongyao.jin over 2 years ago in reply to Sikai Lu

Expert 1220 points

1. I modefi the generate .h file in ti-processor-sdk-rtos-j721e-evm-07_03_00_07\pdk_jacinto_07_03_00_29\packages\ti\drv\sciclient\soc\V1 folder , and rebuild pdklib failed , so i think it compiled these files when build tiboot3

2. sciclient_defaultBoardcfg_rm.c dsp_c66_0 decrease the channel to 6

/*
 * K3 System Firmware Resource Management Configuration Data
 * Auto generated from K3 Resource Partitioning tool
 *
 * Copyright (c) 2018-2021, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/**
 *  \file V1/sciclient_defaultBoardcfg.c
 *
 *  \brief File containing the boardcfg default data structure to
 *      send TISCI_MSG_BOARD_CONFIG message.
 *
 */
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_hosts.h>
#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_boardcfg_constraints.h>
#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_devices.h>
#include <ti/drv/sciclient/soc/V1/sciclient_defaultBoardcfg.h>

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

#if defined (BUILD_MCU1_0)
const struct tisci_local_rm_boardcfg gBoardConfigLow_rm
__attribute__(( aligned(128), section(".boardcfg_data") )) =
{
    .rm_boardcfg = {
        .rev = {
            .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
            .tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE,
        },
        .host_cfg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
                .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_host_cfg),
            },
            .host_cfg_entries = {
                {
                    .host_id = TISCI_HOST_ID_MCU_0_R5_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MCU_0_R5_2,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_A72_2,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_A72_3,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_C7X_1,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_C6X_0_1,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_C6X_1_1,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
            },
        },
        .resasg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
                .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
            },
            .resasg_entries_size = 420 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
        },
    },
    .resasg_entries = {
        {
            .num_resource = 93,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_C66SS0_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 4,
            .host_id = TISCI_HOST_ID_C6X_0_1,
        },
        {
            .num_resource = 93,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_C66SS1_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 4,
            .host_id = TISCI_HOST_ID_C6X_1_1,
        },
        {
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_CMPEVENT_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_LVL_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_LVL_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 32,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 24,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_PLS_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 24,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN2MCU_PLS_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 8,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 16,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 28,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 32,
            .host_id = TISCI_HOST_ID_C6X_0_1,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 36,
            .host_id = TISCI_HOST_ID_C6X_1_1,
        },
        {
            .num_resource = 12,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 40,
            .host_id = TISCI_HOST_ID_A72_2,
        },
        {
            .num_resource = 12,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 52,
            .host_id = TISCI_HOST_ID_A72_3,
        },
        {
            .num_resource = 128,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_R5FSS0_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 128,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_R5FSS0_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 128,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
        },
        {
            .num_resource = 128,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_R5FSS1_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
        },
        {
            .num_resource = 128,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_R5FSS1_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 128,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
        },
        {
            .num_resource = 48,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_TIMESYNC_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 8,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 16,
            .host_id = TISCI_HOST_ID_A72_2,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 22,
            .host_id = TISCI_HOST_ID_A72_3,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 28,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_WKUP_GPIOMUX_INTRTR0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 30,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
        },
        {
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_MODSS_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1024,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_MODSS_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
            .start_resource = 20480,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_MODSS_INTAGGR_1, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1024,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_MODSS_INTAGGR_1, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
            .start_resource = 22528,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 86,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 38,
            .host_id = TISCI_HOST_ID_A72_2,
        },
        {
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 124,
            .host_id = TISCI_HOST_ID_A72_3,
        },
        {
            .num_resource = 12,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 156,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
        },
        {
            .num_resource = 12,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_NAVSS0_UDMASS_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 168,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
        },
        {
            .num_resource = 12,
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            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 8,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 11,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 14,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 17,
            .host_id = TISCI_HOST_ID_C7X_1,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_C6X_0_1,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 23,
            .host_id = TISCI_HOST_ID_C6X_1_1,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 26,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 29,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 48,
            .host_id = TISCI_HOST_ID_A72_2,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 56,
            .host_id = TISCI_HOST_ID_A72_3,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 60,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 68,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 72,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 76,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 80,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 88,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 92,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 256,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
            .start_resource = 56320,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 2,
            .host_id = TISCI_HOST_ID_A72_2,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 6,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 0,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 6,
            .host_id = TISCI_HOST_ID_A72_3,
        },
        {
            .num_resource = 0,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 8,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 8,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 9,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 10,
            .host_id = TISCI_HOST_ID_C7X_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 11,
            .host_id = TISCI_HOST_ID_C6X_0_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 12,
            .host_id = TISCI_HOST_ID_C6X_1_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 13,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 14,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
        },
        {
            .num_resource = 9,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 15,
            .host_id = TISCI_HOST_ID_A72_2,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_A72_3,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 30,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 33,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 35,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 36,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 37,
            .host_id = TISCI_HOST_ID_C7X_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 38,
            .host_id = TISCI_HOST_ID_C6X_0_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 39,
            .host_id = TISCI_HOST_ID_C6X_1_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 40,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 42,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 43,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 0,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 2,
            .host_id = TISCI_HOST_ID_A72_2,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 6,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 0,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 6,
            .host_id = TISCI_HOST_ID_A72_3,
        },
        {
            .num_resource = 0,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 8,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 8,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 9,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 10,
            .host_id = TISCI_HOST_ID_C7X_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 11,
            .host_id = TISCI_HOST_ID_C6X_0_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 12,
            .host_id = TISCI_HOST_ID_C6X_1_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 13,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 14,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
        },
        {
            .num_resource = 9,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 15,
            .host_id = TISCI_HOST_ID_A72_2,
        },
        {
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_A72_3,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 30,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 33,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 35,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 36,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 37,
            .host_id = TISCI_HOST_ID_C7X_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 38,
            .host_id = TISCI_HOST_ID_C6X_0_1,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 39,
            .host_id = TISCI_HOST_ID_C6X_1_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 40,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 42,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_2,
        },
        {
            .num_resource = 3,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 43,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 0,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_UDMAP_0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 20,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_INTR_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 12,
            .host_id = TISCI_HOST_ID_MCU_0_R5_0,
        },
        {
            .num_resource = 28,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_NAVSS0_INTR_0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
            .start_resource = 36,
            .host_id = TISCI_HOST_ID_MCU_0_R5_2,
        },
    }
};
#endif

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Hi,

But are you using SBL boot flow or SPL? Because if you are using SPL, then this needs to be changed in the k3-resource partition tool.

Please follow steps mentioned on below link for SPL or SBL bootflow.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1097038/faq-tda4vm-workflow-and-resource-allocation-build-flow-for-sysconfig-tool

Regards,

Brijesh

0 Sikai Lu over 2 years ago in reply to Brijesh Jadav

TI__Expert 3241 points

Dear Brijesh,

They are using SBL and this is what they did.

hongyao.jin said:
1. i increase DSP C66_0 UDMA channel count to 14 in sysconfig , and get sciclient_defaultBoardcfg_rm.c

2. update sciclient_defaultBoardcfg_rm.c in PSDKQA\PDK\packages\ti\drv\sciclient\soc\V1 folder

make sciclient_boardcfg -sj4

make sciclient_boardcfg BUILD_HS=yes -sj4

3. rebuild tiboot3.bin and replace in emmc

but error (VINTR alloc failed ) still occurred

Sikai

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

SBL mode and make by step 3, but it failed function is Udma_rmAllocVintr, so whether this is caused by the number of interrupts

0 Sikai Lu over 2 years ago in reply to hongyao.jin

TI__Expert 3241 points

Dear Brijesh,

Update from Customer side:

When he changes channel counts, it will show "VINTR alloc failed "

However when he changes channels block-copy then "alloc failed" error disappers while it stps at "Udma_rmAllocVintr"

1. Could you help check we do the modification at right position?

2. They have increased the channels so they think now the problem is the lack of interrupts. Do you mean we can also change the interrupts in Sysconfig? Or even when we change the channel number we have already increase the number of interrupts?

Brijesh Jadav said:
You could allocate more interrupts in the resource manager. But why do you require more than 8 interrupts on C6x? Can you please try using shared interrupts, instead of exclusive interrupts?

You could use shared event and then can use master Event handler as shown below.

cqEventPrms.eventMode = UDMA_EVENT_MODE_SHARED;
cqEventPrms.masterEventHandle = Udma_eventGetGlobalHandle(drvHandle);

Sikai

0 hongyao.jin over 2 years ago in reply to Sikai Lu

Expert 1220 points

1. i want know how to increase interrupts count

2. i try use share interrupt , but i find it still call Udma_rmAllocVintr(drvHandle) and eventHandle->vintrNum is invalid

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Strange, let me spend sometime today to see where it allocates and why it tries to allocate new VIntr.

Rgds,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

hi,

i know what cause this , i must assign value to eventPrms->masterEventHandle, and now it work

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

I thought you are already using master event handler from below statement. isn't it?

The second statement asks UDMA driver to use common master event handle even for this new event, so it should not now allocate new event and should work fine..

cqEventPrms.eventMode = UDMA_EVENT_MODE_SHARED;
cqEventPrms.masterEventHandle = Udma_eventGetGlobalHandle(drvHandle);

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

yes, now it work fine by modefi to share interrupt, and i also want know how to increase interrupts count by sysconfig tool, I can't find the corresponding modification item

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Hi,

You require to increase both of these numbers in order to increase number of virtual interrupt for a core. Below is the number of virtual interrupts supported on mcu2_0 on TDA4VM.

In order to allocate it more for mcu2_0, you require to reduce it from the other core and allocate it for mcu2_0.

But i would not recommend using separate virtual interrupt for each channel. If you dont want to use global virtual interrupt, you could allocate one and share it for all the channels.

In order to allocate virtual master even handler, you could use below code,

/* Alloc VINTR - By registering Master event in Shared mode */
UdmaEventPrms_init(&eventPrms);
eventPrms.eventType = UDMA_EVENT_TYPE_MASTER;
eventPrms.eventMode = UDMA_EVENT_MODE_SHARED;
eventPrms.masterEventHandle = NULL;
retVal = Udma_eventRegister(drvHandle, eventHandle, &eventPrms);

and then for the rest of channels, you could reuse this virtual interrupt for completion event, as shown below.

UdmaEventPrms_init(&cqEventPrms);
cqEventPrms.eventType = UDMA_EVENT_TYPE_DMA_COMPLETION;
cqEventPrms.eventMode = UDMA_EVENT_MODE_SHARED;
cqEventPrms.chHandle = chHandle;
cqEventPrms.masterEventHandle = eventHandle;
cqEventPrms.eventCb = &App_udmaEventDmaCb;
retVal = Udma_eventRegister(drvHandle, cqEventHandle, &cqEventPrms);

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

hi,

after i modefi udma channel count and interrupt count , i rebuild tiboot3.bin and repace it in emmc , and the modefication work,

but i find after i replace the tiboot3 , if i abort autoboot in uboot satrtup, after about 25 seconds, the board will restart

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Hi,

This does not seem to be related to the changes in the resource manager.

Was this working fine for longer duration without this change? Also after this change, if you enable autoboot in uboot and boot Linux, does it run fine for longer duration?

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

hi,

This problem may be caused by our application. I need to confirm it

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Sure, please let us know if there is any update.

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

hi, It has been confirmed that our app caused the problem

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Thanks, let us know if there is any further question, otherwise, please close this ticket.

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

hi,

we have problems using UDMA, example of reference is appUdmaTestNDCopy() function in vision_apps\utils\udma\src\app_udma_test.c

i want know what should I modefi if I want to use shared interrupts

i find Udma_eventRegister() is called three times in appUdmaCreateCh() function, which one do I need to modify

0 hongyao.jin over 2 years ago in reply to hongyao.jin

Expert 1220 points

Anyway, can we use shared interrupts with NDcopy

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Not sure why shared interrupts not used for ND Copy. Are you facing any issue with it? Can you try using shared even for it also?

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

1. I tested the share interrupt using appUdmaTestNDCopy() in the vision_app app_udma_test.c.

2. I modefi the eventPrms->eventMode to UDMA_EVENT_MODE_SHARED, modefi eventPrms->masterEventHandle to Udma_eventGetGlobalHandle(ch_obj->drv_handle).

3. i have no found callback function for TR event, so eventCb and appData is set to NULL.

4. When I run the demo, appUdmaCopyNDWait was not return

Is my modification correct, or did I miss something

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Hi,

Not sure why this is not working. For the time being, can you please continue using exclusive event for ND copy?

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

when i reuse exclusive event for ND copy , it work , can you test the share mode

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Hi,

Not sure why it is not working. I have raised this issue with our team.

https://jira.itg.ti.com/browse/ADASVISION-5787

Regards,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

hi.

When I added a callback function I wrote myself, it turned out that the callback function was triggered every time appUdmaCopyNDTrigger was called.

So, I set the flag bit in the callback function and modified the break judgment condition of the appUdmaCopyNDWait function, in which case appUdmaTestNDCopy runs fine

I hope this test will be helpful to your analysis, or whether I can operate in this way and whether it is safe

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

But then there is no issue, isn't it? callback function needs to be provided to unblock main task..

Rgds,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

yes it is , but whether it's reasonable for me to do this., I'm worried about errors when multiple channels operate at the same time

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

Yes, it is completely ok. I see you are already passing ch_obj as appData and this is being accessed from the callback function. So even in case of multi-channels, it would work fine and process/unblock correct channel/task.

Rgds,

Brijesh

0 hongyao.jin over 2 years ago in reply to Brijesh Jadav

Expert 1220 points

hi,

When the

appUdmaTestNDCopy function finished, we used the appUdmaCopyDelete function to free the channel resource and found that we could not exit the Udma_ringFlushRaw function

0 hongyao.jin over 2 years ago in reply to hongyao.jin

Expert 1220 points

tempRetVal is -2

0 Brijesh Jadav over 2 years ago in reply to hongyao.jin

TI__Guru**** 477555 points

This error essentially means bad args ie null pointer.. Which means either ringHandle is incorrect or ring number is incorrect. Can you please check the parameter that are passed to this function? is the getFqRingHandle returning correct ringHandle?

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TDA4VM: DSP C6x_1 UDMA VINTR alloc failed