Power Sequencing

The power sequence requirements are shown in the data manual.  There are many industry solutions for sequencing itself.  You may want to look at the implementation on the C6678 EVM (same power sequence) for reference.

Best Regards,

Chad

 I did see the c6678 EVM Board document and on pg 4 is the power sequence. However, the power sequence just state that what needs to be power first, then followed by what, etc. For C6678 (as well as other c66), the power sequence is 

1. CVDD
2. CVDD1, VDDT1-3
3. DVDD18, AVDD1, AVDD2 (HHV)
4. DVDD18, VDDR1-6 

Of course this is the core before IO power sequencing but there is also a IO before core sequencing as well, as detailed in the datasheet.

However, what I wish to know is the implementation details. How to power up CVDD first, followed by CVDD1, VDDT1-3 after some millisec, etc. Is there a chip to do that or do the user needs to figure out some state machine to do so? If there is a chip, is there any recommendation?

Another thing to clarify is the SmartReflex and power sequence are not the same thing, right? Cos, I know how to implement SmartReflex from the c6678 EVM board document  by using UCD7242 and UCD9222 and some other power regulator, but I still dont know how to implement power sequence after reading the c6678 EVM board document. SmartReflex is to save power whereas power sequence is to power the DSP chip in the right order for the DSP chip to function properly.

First time dealing with DSP chip and power sequencing, hence not sure about the implementation. Thanks for taking time to reply

I realize that the EVM document did mention how it performs power sequencing. It uses FPGA to do power sequencing and other functions.