This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
Can you please help us understand why you want to move VPAC to mcu2_1? On the other ticket, you mentioned that you want to move DMPAC to mcu2_0. Could you help us understand why you want to swap cores for VPAC and DMPAC?
Regards,
Brijesh
Our system usually uses VHWA_VPAC and eDP, but not DMPAC and CODEC.
The system has four camera-related applications.
VPAC and eDP run on mcore 2_0
So I want VPAC to move to Core 2_1.
Because I want to reduce the load on core2_0.
ok, can you please follow the patches that i shared earlier and make similar changes for VPAC to move from mcu2_0 to mcu2_1?
I think PDK driver does support VPAC on mcu2_1. We just need to move it in the tiovx and vision apps and also allocate the VPAC channels on mcu2_1..
Regards,
Brijesh
hi i can't apply your patch file
because i have not rm-cfg.c file
our system use pdk 7.1 version
can you check this please
Hi,
One questions, what else is running on mcu2_0? Because if you are just using VPAC and eDP display via DSS, it shouldn't cause load on the mcu2_0. How much is the currently load you are seeing on mcu2_0 with VPAC and eDP?
Also which bootflow are you using on SDK7.1? Are you using QNX on A72? If yes, how are you booting QNX on A72? Is it using SBL or uboot?
Regards,
Brijesh
hi
i don't know how much load mcu2_0
An experiment is being conducted to check whether a load is generated when processing a camera image.
Runs multiple camera image processing applications.
Frame drops are occurring.
I want to check if this is due to the load of mcu2_0.
i use A72 QNX and SBL booting thank you
Hi,
Can you please print the performance stats while running OpenVX example and share it with us? This will help to understand the load on mcu2_0 and which component is causing this load?
Regards,
Brijesh
It's not a openVX example.
We are developing an ADAS project.
and can you tell me how to print performance stats
in A72 QNX SBL booting mode
please tell me how to config another way rm-cfg.c file
Can you please refer to the steps mentioned in the below link? Essentially you need to move external channels for Hwa from mcu2_0 to mcu2_1..
Regards,
Brijesh
Hello.
i did Install the sysconfig application
And I can't find the psdkla folder.
Does this mean psdkqa?
even if this mean psdkqa but i can't find board-support/k3-respart-tool folder
Hi,
Please install PSDKLA from https://www.ti.com/tool/download/PROCESSOR-SDK-RTOS-J721E/07.01.00.11
Regards,
Brijesh
Hello.
I downloaded all the packages from the link you guided me.
However, the board support folder and the psdkla folder could not be found.
The board-support folder appears to be on the Linux SDK, but my system is using QNX.
I know it's inconvenient for you, but could you tell me in more detail?
Hi,
Please download and install PSDKLA from the above link, ie https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-bA0wfI4X2g/07.01.00.11/ti-processor-sdk-rtos-j721e-evm-07_01_00_11-linux-x64-installer.run
After installation is complete, please run setup.sh script.
Once above both steps are complete, then you will see board-support folder.
Regards,
Brijesh
I downloaded ti-linux-rtos-j721e-evm-07_01_00_11-linux-x64-run.
And I installed "ti-processor-sdk-rtos-j721e-evm-07_01_00_11"
However, the file "setup.sh" could not be found
Did I do anything wrong?
You can find it in ti-processor-sdk-rtos-j721e-evm-07_01_00_11 folder.
Regards,
Brijesh
No, there is no file.
I downloaded ti-processor-sdk-linux-rt-j7-evm-08_00_08.
Here's the setup.sh you said.
It is not in the ti-processor-sdk-rtos-j721e-evm-07_01_00_11.
Hi,
As i mentioned earlier, this file is available in the psdkla, not in psdkra..
Also it seems you are using linux-rt. Please use non-rt version of the Linux.
Regards,
Brijesh
please check i mentioned earlier....
and i just say "setup.sh" file is not exist in ti-processor-sdk-rtos-j721e-evm-07_01_00_11....
i no use linux-rt version
Hi,
setup.sh script helps to setup the environment and toolchains. It is available in the psdkla, ie in ti-processor-sdk-linux.... component.
It is not available in psdkra ie ti-processor-sdk-rtos.....
Once you run setup.sh script in psdkla, you will able to find related scripts in board-support folder..
Regards,
Brijesh
you mentioned ago
this link download file is psdkra
could you check this?
if this is right could you give me download link psdkla?
oh sorry, i missed it. PSDKLA download link is at https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-U6uMjOroyO/07.01.00.10/ti-processor-sdk-linux-j7-evm-07_01_00_10-Linux-x86-Install.bin
Regards,
Brijesh
Hello.
An error occurred while performing the last step of the staff you guided below.
"Finally, click the Browse button to open the existing design of the platform of interest. board-support\k3-respart-tool\out\j721e-evm.Navigate to the syscfg directory to find the platform's baseline file. Use this as a starting point for customization."
What should I do?
Hi,
Have you followed the exact steps mentioned on below link? Essentially, after installing sysconfig tool, you need to run setup.py script and give the path to sysconfig installer path.
Regards,
Brijesh
I ran the setup.py script but encountered the above problem, so I looked at the link below and tried to solve the problem.
I was successful in opening the j721e-evm.syscfg file with the sysconfig application, but after the program opened the config file, it did not respond to anything. No matter where I click, there is no response.
I understand that your intention is to move the VPAC function of MCU2_0 to MCU2_1 and generate the code by configuring UDMA and memory config through the sysconfig application. If you want to move the VPAC function of MCU2_0 to MCU2_1 and move the DMPAC function of MCU2_1 to MCU2_0, can you tell me how to configure it?
I think the previous question can be solved using CSS Studio.
Hi
Could you please tell me exactly what you want to do? I will share you the changes on SDK08.05 release.
Is it VPAC on mcu2_1 and DMPAC on mcu2_0?
Regards,
Brijesh
I would like to run VPAC which is running on MCU2_0 on MCU2_1.
And I am curious about how to set resources such as UDMA.
For example, I am curious about the content of allocating the number of UDMA TX resources in the attached patch content moving DMPAC to 2_0 as you previously mentioned.
Previous mention >
e2e.ti.com/.../tda4vm-tda4vm-can-we-move-vhwa-dmpac-from-mcu2_1-to-mcu2_0
hi,
And I am curious about how to set resources such as UDMA.
For example, I am curious about the content of allocating the number of UDMA TX resources in the attached patch content moving DMPAC to 2_0 as you previously mentioned.
Specifically for the above question, please change DMA channels for HWA from mcu2_0 to mcu2_1.
By default mcu2_0 has 96 HWA channels, starting from 172 and mcu2_1 has 32, starting from 268.
mcu2_0
mcu2_1
Please interchange start and number of channels for both the cores and then regenerate board config file and rebuild PDK components and SBL.
Regards,
Brijesh
As instructed, I applied the relevant information in sciclient_defaultboardcfg_rm.c, built it, and applied the built SBL. LDC, MSC, and NF were successfully initialized, but an error occurred in VISS. Do you have any advice?
[MCU2_1] 7.698026 s: MEM: Init ... !!!
[MCU2_1] 7.698059 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!!
[MCU2_1] 7.698108 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!!
[MCU2_1] 7.698153 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce010000 of size 67043328 bytes !!!
[MCU2_1] 7.698196 s: MEM: Init ... Done !!!
[MCU2_1] 7.698213 s: FVID2: Init ... !!!
[MCU2_1] 7.698264 s: FVID2: Init ... Done !!!
[MCU2_1] 7.698290 s: VHWA: VPAC Init ... !!!
[MCU2_1] 7.698309 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_1] 7.698405 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1] 7.698434 s: VHWA: LDC Init ... !!!
[MCU2_1] 7.701141 s: VHWA: LDC Init ... Done !!!
[MCU2_1] 7.701191 s: VHWA: MSC Init ... !!!
[MCU2_1] 7.711538 s: VHWA: MSC Init ... Done !!!
[MCU2_1] 7.711582 s: VHWA: NF Init ... !!!
[MCU2_1] 7.713009 s: VHWA: NF Init ... Done !!!
[MCU2_1] 7.713052 s: VHWA: VISS Init ... !!!
[MCU2_1] 7.714655 s: [UDMA]
[MCU2_1] 7.714691 s: [Error] CQ ring alloc failed!!!
[MCU2_1] 7.714728 s: [UDMA]
[MCU2_1] 7.714743 s: [Error] Channel resource allocation failed!!
[MCU3_0] 12.641570 s: CIO: Init ... Done !!!
Hi,
ok, now it is running out of free rings. I think we need to increase number of rings for mcu2_1.
Can you please move few rings from mcu2_0 to mcu2_1?
Regards,
Brijesh
As mentioned, the ring buffer was adjusted. However, the RAM related logs and UDMA copy init failed in the ENC (DMPAC has been turned off). Please refer to the attached log VPACMCU2_1.log.
When DMPAC was moved to MCU2_0, the same situation occurred as before. The value of extend TX Channels for HWA count was set to 32 in 2_0, but it still occurred. Please refer to the attached log DMPACMCU2_0.log.
[MCU2_0] 7.587850 s: CIO: Init ... Done !!! [MCU2_0] 7.587921 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_0] 7.587960 s: APP: Init ... !!! [MCU2_0] 7.587978 s: SCICLIENT: Init ... !!! [MCU2_0] 7.588156 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU2_0] 7.588191 s: SCICLIENT: DMSC FW revision 0x14 [MCU2_0] 7.588215 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_0] 7.588239 s: SCICLIENT: Init ... Done !!! [MCU2_0] 7.588261 s: UDMA: Init ... !!! [MCU2_0] 7.589172 s: UDMA: Init ... Done !!! [MCU2_0] 7.589221 s: MEM: Init ... !!! [MCU2_0] 7.589256 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!! [MCU2_0] 7.589312 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!! [MCU2_0] 7.589362 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 65536 bytes !!! [MCU2_0] 7.589408 s: MEM: Init ... Done !!! [MCU2_0] 7.589428 s: FVID2: Init ... !!! [MCU2_0] 7.589477 s: FVID2: Init ... Done !!! [MCU2_0] 7.589498 s: IPC: Init ... !!! [MCU2_0] 7.589525 s: IPC: 8 CPUs participating in IPC !!! [MCU2_0] 7.596486 s: IPC: Init ... Done !!! [MCU2_0] 7.596542 s: APP: Syncing with 7 CPUs ... !!! [MCU2_0] 12.719182 s: APP: Syncing with 7 CPUs ... Done !!! [MCU2_0] 12.719217 s: REMOTE_SERVICE: Init ... !!! [MCU2_0] 12.720853 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_0] 12.720916 s: ETHFW: Init ... !!! [MCU2_0] 12.726423 s: CPSW_9G Test on MAIN NAVSS [MCU2_0] 12.740296 s: ETHFW: Version : 0.01.01 [MCU2_0] 12.740358 s: ETHFW: Build Date: Feb 3, 2023 [MCU2_0] 12.740387 s: ETHFW: Build Time: 11:07:50 [MCU2_0] 12.740409 s: ETHFW: Commit SHA: e7b944fe [MCU2_0] 12.740435 s: ETHFW: Init ... DONE !!! [MCU2_0] 12.740458 s: ETHFW: Remove server Init ... !!! [MCU2_0] 12.741651 s: Remote demo device (core : mcu2_0) ..... [MCU2_0] 12.741710 s: ETHFW: Remove server Init ... DONE !!! [MCU2_0] 12.748976 s: Host MAC address: 70:ff:76:1d:92:c2 [MCU2_0] 12.790946 s: APP: Setup Dual Vout !!! [MCU2_0] 12.832955 s: APP: Setup Dual Vout (0)... !!! [MCU2_0] 12.919050 s: [Log] DssDsiI2c Initialize [MCU2_0] 13.019089 s: I2c Varify d Error Address = 29, Value = 0 [MCU2_0] 13.119087 s: I2c Varify d Error Address = 33, Value = 0 [MCU2_0] 13.402091 s: I2c Varify d Error Address = 7054, Value = 0 [MCU2_0] 13.661638 s: I2c Varify d Error Address = 7a14, Value = 0 [MCU2_0] 13.916092 s: I2c Varify d Error Address = 6420, Value = 0 [MCU2_0] 14.171350 s: I2c Varify d Error Address = 6420, Value = 0 [MCU2_0] 14.257057 s: [Log] DssDsiI2c Initialize max96717 [MCU2_0] 14.458087 s: I2c Varify d Error Address = 10, Value = 11 [MCU2_0] 14.544054 s: [INFO] DssDsiI2c Initialize max9295D [MCU2_0] 14.653463 s: I2c Varify d Error Address = 10, Value = 1 [MCU2_0] 14.653527 s: Serializer Done [MCU2_0] 14.653558 s: VX_ZONE_INIT:Enabled [MCU2_0] 14.653582 s: VX_ZONE_ERROR:Enabled [MCU2_0] 14.653602 s: VX_ZONE_WARNING:Enabled [MCU2_0] 14.654616 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target IPU1-0 [MCU2_0] 14.654884 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target DMPAC_SDE [MCU2_0] 14.655190 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target DMPAC_DOF [MCU2_0] 14.655472 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE1 [MCU2_0] 14.655754 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE2 [MCU2_0] 14.656085 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target DISPLAY1 [MCU2_0] 14.656385 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target DISPLAY2 [MCU2_0] 14.656659 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CSITX [MCU2_0] 14.656981 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE3 [MCU2_0] 14.657280 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE4 [MCU2_0] 14.657573 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE5 [MCU2_0] 14.657865 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE6 [MCU2_0] 14.658209 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE7 [MCU2_0] 14.658496 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE8 [MCU2_0] 14.658551 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [MCU2_0] 14.658579 s: APP: OpenVX Target kernel init ... !!! [MCU2_0] 14.658717 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_0] 14.658746 s: CSI2RX: Init ... !!! [MCU2_0] 14.658763 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_0] 14.658838 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 14.658867 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2 [MCU2_0] 14.658970 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 14.659004 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2 [MCU2_0] 14.659072 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 14.659097 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2 [MCU2_0] 14.659146 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 14.659170 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2 [MCU2_0] 14.659217 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 14.659834 s: CSI2RX: Init ... Done !!! [MCU2_0] 14.659879 s: CSI2TX: Init ... !!! [MCU2_0] 14.659898 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_0] 14.659993 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 14.660025 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2 [MCU2_0] 14.660090 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 14.660115 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2 [MCU2_0] 14.660171 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 14.660642 s: CSI2TX: Init ... Done !!! [MCU2_0] 14.660680 s: ISS: Init ... !!! [MCU2_0] 14.660735 s: Found sensor OX01D10 at location 0 [MCU2_0] 14.660766 s: IssSensor_Init ... Done !!! [MCU2_0] 14.660832 s: vissRemoteServer_Init ... Done !!! [MCU2_0] 14.660884 s: IttRemoteServer_Init ... Done !!! [MCU2_0] 14.660910 s: UDMA Copy: Init ... !!! [MCU2_0] 14.662278 s: UDMA Copy: Init ... Done !!! [MCU2_0] 14.662328 s: APP: Init ... Done !!! [MCU2_0] 14.662350 s: APP: Run ... !!! [MCU2_0] 14.662367 s: IPC: Starting echo test ... [MCU2_0] 14.665395 s: APP: Run ... Done !!! [MCU2_0] 14.667069 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.] [MCU2_0] 14.667235 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[.] [MCU2_0] 14.667404 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[.] [MCU2_0] 14.667530 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.] [MCU2_0] 14.667689 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] [MCU2_1] 7.547420 s: CIO: Init ... Done !!! [MCU2_1] 7.547485 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_1] 7.547526 s: APP: Init ... !!! [MCU2_1] 7.547544 s: SCICLIENT: Init ... !!! [MCU2_1] 7.547728 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU2_1] 7.547765 s: SCICLIENT: DMSC FW revision 0x14 [MCU2_1] 7.547788 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_1] 7.547812 s: SCICLIENT: Init ... Done !!! [MCU2_1] 7.547833 s: UDMA: Init ... !!! [MCU2_1] 7.548819 s: UDMA: Init ... Done !!! [MCU2_1] 7.548874 s: MEM: Init ... !!! [MCU2_1] 7.548907 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!! [MCU2_1] 7.548960 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!! [MCU2_1] 7.549007 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce010000 of size 67043328 bytes !!! [MCU2_1] 7.549049 s: MEM: Init ... Done !!! [MCU2_1] 7.549067 s: FVID2: Init ... !!! [MCU2_1] 7.549116 s: FVID2: Init ... Done !!! [MCU2_1] 7.549141 s: IPC: Init ... !!! [MCU2_1] 7.549170 s: IPC: 8 CPUs participating in IPC !!! [MCU2_1] 7.556031 s: IPC: Init ... Done !!! [MCU2_1] 7.556085 s: APP: Syncing with 7 CPUs ... !!! [MCU2_1] 12.719181 s: APP: Syncing with 7 CPUs ... Done !!! [MCU2_1] 12.719217 s: REMOTE_SERVICE: Init ... !!! [MCU2_1] 12.720726 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_1] 12.720788 s: VHWA: VPAC Init ... !!! [MCU2_1] 12.720812 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2 [MCU2_1] 12.720914 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 12.720978 s: VHWA: LDC Init ... !!! [MCU2_1] 12.725875 s: VHWA: LDC Init ... Done !!! [MCU2_1] 12.725960 s: VHWA: MSC Init ... !!! [MCU2_1] 12.736356 s: VHWA: MSC Init ... Done !!! [MCU2_1] 12.736408 s: VHWA: NF Init ... !!! [MCU2_1] 12.738395 s: VHWA: NF Init ... Done !!! [MCU2_1] 12.738439 s: VHWA: VISS Init ... !!! [MCU2_1] 12.746869 s: VHWA: VISS Init ... Done !!! [MCU2_1] 12.746945 s: VHWA: VPAC Init ... Done !!! [MCU2_1] 12.746978 s: VHWA: Codec: Init ... !!! [MCU2_1] 12.747000 s: VHWA: VDEC Init ... !!! [MCU2_1] 12.760050 s: VHWA: VDEC Init ... Done !!! [MCU2_1] 12.760101 s: VHWA: VENC Init ... !!! [MCU2_1] 12.760216 s: MM_ENC_Init: No OCM RAM pool available, fallback to DDR mode for above mp params [MCU2_1] 12.800457 s: VHWA: VENC Init ... Done !!! [MCU2_1] 12.800507 s: VHWA: Init ... Done !!! [MCU2_1] 12.800542 s: VX_ZONE_INIT:Enabled [MCU2_1] 12.800568 s: VX_ZONE_ERROR:Enabled [MCU2_1] 12.800588 s: VX_ZONE_WARNING:Enabled [MCU2_1] 12.801554 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_NF [MCU2_1] 12.801774 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_LDC1 [MCU2_1] 12.802024 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_MSC1 [MCU2_1] 12.802255 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_MSC2 [MCU2_1] 12.802497 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_VISS1 [MCU2_1] 12.802715 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VDEC1 [MCU2_1] 12.802943 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VDEC2 [MCU2_1] 12.803162 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VENC1 [MCU2_1] 12.803368 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VENC2 [MCU2_1] 12.803596 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_CE_VISS [MCU2_1] 12.806148 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_CE_RC [MCU2_1] 12.806194 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [MCU2_1] 12.806221 s: APP: OpenVX Target kernel init ... !!! [MCU2_1] 12.852102 s: [TWEAK_STUB.INIT] Tweak is not compiled-in [MCU2_1] 12.852155 s: [STORAGE_TRACE.INIT] Trace is not compiled-in [MCU2_1] 12.852683 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_1] 12.852722 s: UDMA Copy: Init ... !!! [MCU2_1] 12.852830 s: [UDMA] [MCU2_1] 12.852857 s: [Error] RM Alloc Blkcpy Ch failed!!! [MCU2_1] 12.852888 s: [UDMA] [MCU2_1] 12.852900 s: [Error] Channel resource allocation failed!! [MCU2_1] 12.852955 s: UDMA : ERROR: UDMA channel open failed!! [MCU2_1] 12.853019 s: UDMA : ERROR: Default channel object create failed!!! [MCU2_1] 12.853053 s: UDMA Copy: Init ... Done !!! [MCU3_0] 12.427478 s: CIO: Init ... Done !!! [MCU3_0] 12.427550 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU3_0] 12.427594 s: APP: Init ... !!! [MCU3_0] 12.427614 s: SCICLIENT: Init ... !!! [MCU3_0] 12.427802 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU3_0] 12.427843 s: SCICLIENT: DMSC FW revision 0x14 [MCU3_0] 12.427868 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU3_0] 12.427894 s: SCICLIENT: Init ... Done !!! [MCU3_0] 12.427915 s: MEM: Init ... !!! [MCU3_0] 12.427943 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3c00000 of size 2097152 bytes !!! [MCU3_0] 12.427994 s: MEM: Init ... Done !!! [MCU3_0] 12.428013 s: IPC: Init ... !!! [MCU3_0] 12.428040 s: IPC: 8 CPUs participating in IPC !!! [MCU3_0] 12.434906 s: IPC: Init ... Done !!! [MCU3_0] 12.434964 s: APP: Syncing with 7 CPUs ... !!! [MCU3_0] 12.719182 s: APP: Syncing with 7 CPUs ... Done !!! [MCU3_0] 12.719220 s: REMOTE_SERVICE: Init ... !!! [MCU3_0] 12.720755 s: REMOTE_SERVICE: Init ... Done !!! [MCU3_0] 12.720815 s: APP: Init ... Done !!! [MCU3_0] 12.720847 s: APP: Run ... !!! [MCU3_0] 12.720871 s: IPC: Starting echo test ... [MCU3_0] 12.723702 s: APP: Run ... Done !!! [MCU3_0] 12.724544 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_0] 12.724728 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_0] 12.726697 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[.] C66X_2[P] C7X_1[P] [MCU3_0] 12.726995 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] [MCU3_0] 14.666825 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] [MCU3_1] 12.490487 s: CIO: Init ... Done !!! [MCU3_1] 12.490560 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU3_1] 12.490604 s: APP: Init ... !!! [MCU3_1] 12.490624 s: SCICLIENT: Init ... !!! [MCU3_1] 12.490808 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU3_1] 12.490849 s: SCICLIENT: DMSC FW revision 0x14 [MCU3_1] 12.490876 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU3_1] 12.490902 s: SCICLIENT: Init ... Done !!! [MCU3_1] 12.490923 s: MEM: Init ... !!! [MCU3_1] 12.490950 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3e00000 of size 2097152 bytes !!! [MCU3_1] 12.490999 s: MEM: Init ... Done !!! [MCU3_1] 12.491018 s: IPC: Init ... !!! [MCU3_1] 12.491046 s: IPC: 8 CPUs participating in IPC !!! [MCU3_1] 12.497918 s: IPC: Init ... Done !!! [MCU3_1] 12.497975 s: APP: Syncing with 7 CPUs ... !!! [MCU3_1] 12.719182 s: APP: Syncing with 7 CPUs ... Done !!! [MCU3_1] 12.719218 s: REMOTE_SERVICE: Init ... !!! [MCU3_1] 12.720718 s: REMOTE_SERVICE: Init ... Done !!! [MCU3_1] 12.720778 s: APP: Init ... Done !!! [MCU3_1] 12.720806 s: APP: Run ... !!! [MCU3_1] 12.720826 s: IPC: Starting echo test ... [MCU3_1] 12.723612 s: APP: Run ... Done !!! [MCU3_1] 12.724390 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_1] 12.724736 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_1] 12.726694 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[.] C66X_2[P] C7X_1[P] [MCU3_1] 12.726984 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [MCU3_1] 14.666809 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [C6x_1 ] 12.569332 s: CIO: Init ... Done !!! [C6x_1 ] 12.569365 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_1 ] 12.569378 s: APP: Init ... !!! [C6x_1 ] 12.569386 s: SCICLIENT: Init ... !!! [C6x_1 ] 12.569554 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C6x_1 ] 12.569565 s: SCICLIENT: DMSC FW revision 0x14 [C6x_1 ] 12.569574 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_1 ] 12.569583 s: SCICLIENT: Init ... Done !!! [C6x_1 ] 12.569593 s: UDMA: Init ... !!! [C6x_1 ] 12.570626 s: UDMA: Init ... Done !!! [C6x_1 ] 12.570647 s: MEM: Init ... !!! [C6x_1 ] 12.570658 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!! [C6x_1 ] 12.570675 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_1 ] 12.570690 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!! [C6x_1 ] 12.570706 s: MEM: Init ... Done !!! [C6x_1 ] 12.570714 s: IPC: Init ... !!! [C6x_1 ] 12.570726 s: IPC: 8 CPUs participating in IPC !!! [C6x_1 ] 12.574409 s: IPC: Init ... Done !!! [C6x_1 ] 12.574437 s: APP: Syncing with 7 CPUs ... !!! [C6x_1 ] 12.719180 s: APP: Syncing with 7 CPUs ... Done !!! [C6x_1 ] 12.719191 s: REMOTE_SERVICE: Init ... !!! [C6x_1 ] 12.719855 s: REMOTE_SERVICE: Init ... Done !!! [C6x_1 ] 12.719899 s: VX_ZONE_INIT:Enabled [C6x_1 ] 12.719910 s: VX_ZONE_ERROR:Enabled [C6x_1 ] 12.719919 s: VX_ZONE_WARNING:Enabled [C6x_1 ] 12.720803 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_1 ] 12.720822 s: APP: OpenVX Target kernel init ... !!! [C6x_1 ] 12.721107 s: APP: OpenVX Target kernel init ... Done !!! [C6x_1 ] 12.721128 s: UDMA Copy: Init ... !!! [C6x_1 ] 12.724305 s: UDMA Copy: Init ... Done !!! [C6x_1 ] 12.724327 s: APP: Init ... Done !!! [C6x_1 ] 12.724774 s: APP: Run ... !!! [C6x_1 ] 12.724784 s: IPC: Starting echo test ... [C6x_1 ] 12.726353 s: APP: Run ... Done !!! [C6x_1 ] 12.726953 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[.] C7X_1[P] [C6x_1 ] 12.726990 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 12.727020 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 12.727050 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 14.666702 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_2 ] 12.639464 s: CIO: Init ... Done !!! [C6x_2 ] 12.639496 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_2 ] 12.639510 s: APP: Init ... !!! [C6x_2 ] 12.639518 s: SCICLIENT: Init ... !!! [C6x_2 ] 12.639689 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C6x_2 ] 12.639701 s: SCICLIENT: DMSC FW revision 0x14 [C6x_2 ] 12.639710 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_2 ] 12.639720 s: SCICLIENT: Init ... Done !!! [C6x_2 ] 12.639729 s: UDMA: Init ... !!! [C6x_2 ] 12.640772 s: UDMA: Init ... Done !!! [C6x_2 ] 12.640794 s: MEM: Init ... !!! [C6x_2 ] 12.640806 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!! [C6x_2 ] 12.640823 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_2 ] 12.640838 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!! [C6x_2 ] 12.640854 s: MEM: Init ... Done !!! [C6x_2 ] 12.640862 s: IPC: Init ... !!! [C6x_2 ] 12.640874 s: IPC: 8 CPUs participating in IPC !!! [C6x_2 ] 12.644597 s: IPC: Init ... Done !!! [C6x_2 ] 12.644626 s: APP: Syncing with 7 CPUs ... !!! [C6x_2 ] 12.719180 s: APP: Syncing with 7 CPUs ... Done !!! [C6x_2 ] 12.719191 s: REMOTE_SERVICE: Init ... !!! [C6x_2 ] 12.719852 s: REMOTE_SERVICE: Init ... Done !!! [C6x_2 ] 12.719895 s: VX_ZONE_INIT:Enabled [C6x_2 ] 12.719907 s: VX_ZONE_ERROR:Enabled [C6x_2 ] 12.719915 s: VX_ZONE_WARNING:Enabled [C6x_2 ] 12.720789 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_2 ] 12.720808 s: APP: OpenVX Target kernel init ... !!! [C6x_2 ] 12.721103 s: APP: OpenVX Target kernel init ... Done !!! [C6x_2 ] 12.721123 s: UDMA Copy: Init ... !!! [C6x_2 ] 12.724218 s: UDMA Copy: Init ... Done !!! [C6x_2 ] 12.724242 s: APP: Init ... Done !!! [C6x_2 ] 12.724539 s: APP: Run ... !!! [C6x_2 ] 12.724549 s: IPC: Starting echo test ... [C6x_2 ] 12.726036 s: APP: Run ... Done !!! [C6x_2 ] 12.726579 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[.] C66X_2[s] C7X_1[P] [C6x_2 ] 12.726661 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[.] C66X_2[s] C7X_1[P] [C6x_2 ] 12.726715 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[.] C66X_2[s] C7X_1[P] [C6x_2 ] 12.726917 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 14.666747 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C7x_1 ] 12.716275 s: CIO: Init ... Done !!! [C7x_1 ] 12.716298 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [C7x_1 ] 12.716314 s: APP: Init ... !!! [C7x_1 ] 12.716321 s: SCICLIENT: Init ... !!! [C7x_1 ] 12.716475 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C7x_1 ] 12.716488 s: SCICLIENT: DMSC FW revision 0x14 [C7x_1 ] 12.716498 s: SCICLIENT: DMSC FW ABI revision 3.1 [C7x_1 ] 12.716509 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 12.716517 s: UDMA: Init ... !!! [C7x_1 ] 12.716923 s: UDMA: Init ... Done !!! [C7x_1 ] 12.716934 s: MEM: Init ... !!! [C7x_1 ] 12.716944 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!! [C7x_1 ] 12.716965 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!! [C7x_1 ] 12.716983 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!! [C7x_1 ] 12.717000 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!! [C7x_1 ] 12.717017 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 234881024 bytes !!! [C7x_1 ] 12.717035 s: MEM: Init ... Done !!! [C7x_1 ] 12.717043 s: IPC: Init ... !!! [C7x_1 ] 12.717052 s: IPC: 8 CPUs participating in IPC !!! [C7x_1 ] 12.719154 s: IPC: Init ... Done !!! [C7x_1 ] 12.719167 s: APP: Syncing with 7 CPUs ... !!! [C7x_1 ] 12.719180 s: APP: Syncing with 7 CPUs ... Done !!! [C7x_1 ] 12.719191 s: REMOTE_SERVICE: Init ... !!! [C7x_1 ] 12.719442 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 12.719461 s: VX_ZONE_INIT:Enabled [C7x_1 ] 12.719500 s: VX_ZONE_ERROR:Enabled [C7x_1 ] 12.719511 s: VX_ZONE_WARNING:Enabled [C7x_1 ] 12.719805 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C7x_1 ] 12.719818 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 12.719893 s: APP: OpenVX Target kernel init ... Done !!! [C7x_1 ] 12.719906 s: APP: Init ... Done !!! [C7x_1 ] 12.719914 s: APP: Run ... !!! [C7x_1 ] 12.719922 s: IPC: Starting echo test ... [C7x_1 ] 12.720572 s: APP: Run ... Done !!! [C7x_1 ] 12.724368 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s] [C7x_1 ] 12.724482 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s] [C7x_1 ] 12.726445 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[x] C66X_2[P] C7X_1[s] [C7x_1 ] 12.726805 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s] [C7x_1 ] 14.666762 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
[MCU2_0] 7.118664 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_0] 7.118704 s: APP: Init ... !!! [MCU2_0] 7.118721 s: SCICLIENT: Init ... !!! [MCU2_0] 7.118898 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU2_0] 7.118931 s: SCICLIENT: DMSC FW revision 0x14 [MCU2_0] 7.118953 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_0] 7.118975 s: SCICLIENT: Init ... Done !!! [MCU2_0] 7.118995 s: UDMA: Init ... !!! [MCU2_0] 7.119904 s: UDMA: Init ... Done !!! [MCU2_0] 7.119952 s: MEM: Init ... !!! [MCU2_0] 7.119983 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!! [MCU2_0] 7.120036 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!! [MCU2_0] 7.120083 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 65536 bytes !!! [MCU2_0] 7.120126 s: MEM: Init ... Done !!! [MCU2_0] 7.120145 s: FVID2: Init ... !!! [MCU2_0] 7.120195 s: FVID2: Init ... Done !!! [MCU2_0] 7.120216 s: IPC: Init ... !!! [MCU2_0] 7.120243 s: IPC: 8 CPUs participating in IPC !!! [MCU2_0] 7.127210 s: IPC: Init ... Done !!! [MCU2_0] 7.127266 s: APP: Syncing with 7 CPUs ... !!! [MCU2_0] 11.985227 s: APP: Syncing with 7 CPUs ... Done !!! [MCU2_0] 11.985391 s: REMOTE_SERVICE: Init ... !!! [MCU2_0] 11.986960 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_0] 11.987019 s: VHWA: DMPAC: Init ... !!! [MCU2_0] 11.987042 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2 [MCU2_0] 11.987145 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 11.987177 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2 [MCU2_0] 11.987236 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 11.987261 s: VHWA: DOF Init ... !!! [MCU2_0] 11.987486 s: [UDMA] [MCU2_0] 11.987505 s: Assertion @ Line: 1138 in src/udma_rm.c: rmInitPrms->startUtcCh[utcId] >= utcInfo->startCh : failed !!! [MCU2_0] 11.987552 s: [UDMA] [MCU2_0] 11.987567 s: [Error] RM Alloc Ext Ch failed!!! [MCU2_0] 11.987594 s: [UDMA] [MCU2_0] 11.987610 s: [Error] Channel resource allocation failed!! [MCU2_0] 11.987767 s: VHWA: ERROR: DOF Init Failed !!! [MCU2_0] 11.987811 s: VHWA: DMPAC: Init ... Done !!! [MCU2_1] 7.077560 s: CIO: Init ... Done !!! [MCU2_1] 7.077629 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_1] 7.077671 s: APP: Init ... !!! [MCU2_1] 7.077690 s: SCICLIENT: Init ... !!! [MCU2_1] 7.077878 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU2_1] 7.077915 s: SCICLIENT: DMSC FW revision 0x14 [MCU2_1] 7.077940 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_1] 7.077962 s: SCICLIENT: Init ... Done !!! [MCU2_1] 7.077982 s: UDMA: Init ... !!! [MCU2_1] 7.078977 s: UDMA: Init ... Done !!! [MCU2_1] 7.079029 s: MEM: Init ... !!! [MCU2_1] 7.079061 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!! [MCU2_1] 7.079112 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!! [MCU2_1] 7.079156 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce010000 of size 67043328 bytes !!! [MCU2_1] 7.079199 s: MEM: Init ... Done !!! [MCU2_1] 7.079217 s: FVID2: Init ... !!! [MCU2_1] 7.079266 s: FVID2: Init ... Done !!! [MCU2_1] 7.079290 s: IPC: Init ... !!! [MCU2_1] 7.079318 s: IPC: 8 CPUs participating in IPC !!! [MCU2_1] 7.086175 s: IPC: Init ... Done !!! [MCU2_1] 7.086230 s: APP: Syncing with 7 CPUs ... !!! [MCU2_1] 11.985227 s: APP: Syncing with 7 CPUs ... Done !!! [MCU2_1] 11.985383 s: REMOTE_SERVICE: Init ... !!! [MCU2_1] 11.986853 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_1] 11.986912 s: VHWA: VPAC Init ... !!! [MCU2_1] 11.986935 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2 [MCU2_1] 11.987034 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.987062 s: VHWA: LDC Init ... !!! [MCU2_1] 11.991836 s: VHWA: LDC Init ... Done !!! [MCU2_1] 11.991894 s: VHWA: MSC Init ... !!! [MCU2_1] 12.002090 s: VHWA: MSC Init ... Done !!! [MCU2_1] 12.002144 s: VHWA: NF Init ... !!! [MCU2_1] 12.003538 s: VHWA: NF Init ... Done !!! [MCU2_1] 12.003583 s: VHWA: VISS Init ... !!! [MCU2_1] 12.010401 s: VHWA: VISS Init ... Done !!! [MCU2_1] 12.010454 s: VHWA: VPAC Init ... Done !!! [MCU2_1] 12.010480 s: VHWA: Codec: Init ... !!! [MCU2_1] 12.010498 s: VHWA: VDEC Init ... !!! [MCU2_1] 12.023807 s: VHWA: VDEC Init ... Done !!! [MCU2_1] 12.023856 s: VHWA: VENC Init ... !!! [MCU2_1] 12.023971 s: MM_ENC_Init: No OCM RAM pool available, fallback to DDR mode for above mp params [MCU2_1] 12.064273 s: VHWA: VENC Init ... Done !!! [MCU2_1] 12.064322 s: VHWA: Init ... Done !!! [MCU2_1] 12.064358 s: VX_ZONE_INIT:Enabled [MCU2_1] 12.064382 s: VX_ZONE_ERROR:Enabled [MCU2_1] 12.064400 s: VX_ZONE_WARNING:Enabled [MCU2_1] 12.065362 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_NF [MCU2_1] 12.065588 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_LDC1 [MCU2_1] 12.065847 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_MSC1 [MCU2_1] 12.066061 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_MSC2 [MCU2_1] 12.066295 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_VISS1 [MCU2_1] 12.066523 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VDEC1 [MCU2_1] 12.066770 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VDEC2 [MCU2_1] 12.066992 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VENC1 [MCU2_1] 12.067187 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VENC2 [MCU2_1] 12.067413 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_CE_VISS [MCU2_1] 12.069950 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_CE_RC [MCU2_1] 12.069996 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [MCU2_1] 12.070023 s: APP: OpenVX Target kernel init ... !!! [MCU2_1] 12.115794 s: [TWEAK_STUB.INIT] Tweak is not compiled-in [MCU2_1] 12.115848 s: [STORAGE_TRACE.INIT] Trace is not compiled-in [MCU2_1] 12.116376 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_1] 12.116418 s: UDMA Copy: Init ... !!! [MCU2_1] 12.116517 s: [UDMA] [MCU2_1] 12.116542 s: [Error] RM Alloc Blkcpy Ch failed!!! [MCU2_1] 12.116571 s: [UDMA] [MCU2_1] 12.116584 s: [Error] Channel resource allocation failed!! [MCU2_1] 12.116607 s: UDMA : ERROR: UDMA channel open failed!! [MCU2_1] 12.116660 s: UDMA : ERROR: Default channel object create failed!!! [MCU2_1] 12.116729 s: UDMA Copy: Init ... Done !!! [MCU3_0] 11.693543 s: CIO: Init ... Done !!! [MCU3_0] 11.693616 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU3_0] 11.693660 s: APP: Init ... !!! [MCU3_0] 11.693677 s: SCICLIENT: Init ... !!! [MCU3_0] 11.693864 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU3_0] 11.693907 s: SCICLIENT: DMSC FW revision 0x14 [MCU3_0] 11.693931 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU3_0] 11.693957 s: SCICLIENT: Init ... Done !!! [MCU3_0] 11.693979 s: MEM: Init ... !!! [MCU3_0] 11.694008 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3c00000 of size 2097152 bytes !!! [MCU3_0] 11.694059 s: MEM: Init ... Done !!! [MCU3_0] 11.694077 s: IPC: Init ... !!! [MCU3_0] 11.694104 s: IPC: 8 CPUs participating in IPC !!! [MCU3_0] 11.700987 s: IPC: Init ... Done !!! [MCU3_0] 11.701048 s: APP: Syncing with 7 CPUs ... !!! [MCU3_0] 11.985227 s: APP: Syncing with 7 CPUs ... Done !!! [MCU3_0] 11.985265 s: REMOTE_SERVICE: Init ... !!! [MCU3_0] 11.986848 s: REMOTE_SERVICE: Init ... Done !!! [MCU3_0] 11.986910 s: APP: Init ... Done !!! [MCU3_0] 11.986939 s: APP: Run ... !!! [MCU3_0] 11.986961 s: IPC: Starting echo test ... [MCU3_0] 11.990075 s: APP: Run ... Done !!! [MCU3_0] 11.990997 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_0] 11.991103 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_0] 11.992680 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[P] [MCU3_0] 11.992823 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] [MCU3_1] 11.756560 s: CIO: Init ... Done !!! [MCU3_1] 11.756632 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU3_1] 11.756677 s: APP: Init ... !!! [MCU3_1] 11.756698 s: SCICLIENT: Init ... !!! [MCU3_1] 11.756881 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU3_1] 11.756921 s: SCICLIENT: DMSC FW revision 0x14 [MCU3_1] 11.756946 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU3_1] 11.756971 s: SCICLIENT: Init ... Done !!! [MCU3_1] 11.756992 s: MEM: Init ... !!! [MCU3_1] 11.757022 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3e00000 of size 2097152 bytes !!! [MCU3_1] 11.757073 s: MEM: Init ... Done !!! [MCU3_1] 11.757094 s: IPC: Init ... !!! [MCU3_1] 11.757121 s: IPC: 8 CPUs participating in IPC !!! [MCU3_1] 11.764053 s: IPC: Init ... Done !!! [MCU3_1] 11.764110 s: APP: Syncing with 7 CPUs ... !!! [MCU3_1] 11.985228 s: APP: Syncing with 7 CPUs ... Done !!! [MCU3_1] 11.985265 s: REMOTE_SERVICE: Init ... !!! [MCU3_1] 11.986834 s: REMOTE_SERVICE: Init ... Done !!! [MCU3_1] 11.986897 s: APP: Init ... Done !!! [MCU3_1] 11.986927 s: APP: Run ... !!! [MCU3_1] 11.986946 s: IPC: Starting echo test ... [MCU3_1] 11.990044 s: APP: Run ... Done !!! [MCU3_1] 11.990930 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_1] 11.991076 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_1] 11.992690 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[P] [MCU3_1] 11.992835 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [C6x_1 ] 11.835405 s: CIO: Init ... Done !!! [C6x_1 ] 11.835438 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_1 ] 11.835451 s: APP: Init ... !!! [C6x_1 ] 11.835458 s: SCICLIENT: Init ... !!! [C6x_1 ] 11.835631 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C6x_1 ] 11.835642 s: SCICLIENT: DMSC FW revision 0x14 [C6x_1 ] 11.835651 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_1 ] 11.835661 s: SCICLIENT: Init ... Done !!! [C6x_1 ] 11.835670 s: UDMA: Init ... !!! [C6x_1 ] 11.836707 s: UDMA: Init ... Done !!! [C6x_1 ] 11.836728 s: MEM: Init ... !!! [C6x_1 ] 11.836740 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!! [C6x_1 ] 11.836757 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_1 ] 11.836772 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!! [C6x_1 ] 11.836787 s: MEM: Init ... Done !!! [C6x_1 ] 11.836795 s: IPC: Init ... !!! [C6x_1 ] 11.836807 s: IPC: 8 CPUs participating in IPC !!! [C6x_1 ] 11.840492 s: IPC: Init ... Done !!! [C6x_1 ] 11.840520 s: APP: Syncing with 7 CPUs ... !!! [C6x_1 ] 11.985225 s: APP: Syncing with 7 CPUs ... Done !!! [C6x_1 ] 11.985235 s: REMOTE_SERVICE: Init ... !!! [C6x_1 ] 11.985891 s: REMOTE_SERVICE: Init ... Done !!! [C6x_1 ] 11.985939 s: VX_ZONE_INIT:Enabled [C6x_1 ] 11.985950 s: VX_ZONE_ERROR:Enabled [C6x_1 ] 11.985959 s: VX_ZONE_WARNING:Enabled [C6x_1 ] 11.986884 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_1 ] 11.986902 s: APP: OpenVX Target kernel init ... !!! [C6x_1 ] 11.987191 s: APP: OpenVX Target kernel init ... Done !!! [C6x_1 ] 11.987212 s: UDMA Copy: Init ... !!! [C6x_1 ] 11.990178 s: UDMA Copy: Init ... Done !!! [C6x_1 ] 11.990247 s: APP: Init ... Done !!! [C6x_1 ] 11.990463 s: APP: Run ... !!! [C6x_1 ] 11.990477 s: IPC: Starting echo test ... [C6x_1 ] 11.991989 s: APP: Run ... Done !!! [C6x_1 ] 11.992618 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[.] C7X_1[P] [C6x_1 ] 11.992668 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[.] C7X_1[P] [C6x_1 ] 11.992699 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[.] C7X_1[P] [C6x_1 ] 11.992786 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_2 ] 11.905527 s: CIO: Init ... Done !!! [C6x_2 ] 11.905559 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_2 ] 11.905572 s: APP: Init ... !!! [C6x_2 ] 11.905580 s: SCICLIENT: Init ... !!! [C6x_2 ] 11.905747 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C6x_2 ] 11.905759 s: SCICLIENT: DMSC FW revision 0x14 [C6x_2 ] 11.905768 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_2 ] 11.905778 s: SCICLIENT: Init ... Done !!! [C6x_2 ] 11.905787 s: UDMA: Init ... !!! [C6x_2 ] 11.906827 s: UDMA: Init ... Done !!! [C6x_2 ] 11.906848 s: MEM: Init ... !!! [C6x_2 ] 11.906860 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!! [C6x_2 ] 11.906878 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_2 ] 11.906893 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!! [C6x_2 ] 11.906909 s: MEM: Init ... Done !!! [C6x_2 ] 11.906918 s: IPC: Init ... !!! [C6x_2 ] 11.906930 s: IPC: 8 CPUs participating in IPC !!! [C6x_2 ] 11.910651 s: IPC: Init ... Done !!! [C6x_2 ] 11.910680 s: APP: Syncing with 7 CPUs ... !!! [C6x_2 ] 11.985225 s: APP: Syncing with 7 CPUs ... Done !!! [C6x_2 ] 11.985236 s: REMOTE_SERVICE: Init ... !!! [C6x_2 ] 11.985891 s: REMOTE_SERVICE: Init ... Done !!! [C6x_2 ] 11.985938 s: VX_ZONE_INIT:Enabled [C6x_2 ] 11.985949 s: VX_ZONE_ERROR:Enabled [C6x_2 ] 11.985958 s: VX_ZONE_WARNING:Enabled [C6x_2 ] 11.986873 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_2 ] 11.986891 s: APP: OpenVX Target kernel init ... !!! [C6x_2 ] 11.987185 s: APP: OpenVX Target kernel init ... Done !!! [C6x_2 ] 11.987206 s: UDMA Copy: Init ... !!! [C6x_2 ] 11.990071 s: UDMA Copy: Init ... Done !!! [C6x_2 ] 11.990088 s: APP: Init ... Done !!! [C6x_2 ] 11.990554 s: APP: Run ... !!! [C6x_2 ] 11.990578 s: IPC: Starting echo test ... [C6x_2 ] 11.992151 s: APP: Run ... Done !!! [C6x_2 ] 11.992680 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[.] [C6x_2 ] 11.992718 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 11.992832 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 11.992867 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C7x_1 ] 11.982320 s: CIO: Init ... Done !!! [C7x_1 ] 11.982342 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [C7x_1 ] 11.982358 s: APP: Init ... !!! [C7x_1 ] 11.982365 s: SCICLIENT: Init ... !!! [C7x_1 ] 11.982518 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C7x_1 ] 11.982532 s: SCICLIENT: DMSC FW revision 0x14 [C7x_1 ] 11.982542 s: SCICLIENT: DMSC FW ABI revision 3.1 [C7x_1 ] 11.982553 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 11.982561 s: UDMA: Init ... !!! [C7x_1 ] 11.982969 s: UDMA: Init ... Done !!! [C7x_1 ] 11.982980 s: MEM: Init ... !!! [C7x_1 ] 11.982991 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!! [C7x_1 ] 11.983011 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!! [C7x_1 ] 11.983028 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!! [C7x_1 ] 11.983045 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!! [C7x_1 ] 11.983062 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 234881024 bytes !!! [C7x_1 ] 11.983081 s: MEM: Init ... Done !!! [C7x_1 ] 11.983089 s: IPC: Init ... !!! [C7x_1 ] 11.983099 s: IPC: 8 CPUs participating in IPC !!! [C7x_1 ] 11.985198 s: IPC: Init ... Done !!! [C7x_1 ] 11.985212 s: APP: Syncing with 7 CPUs ... !!! [C7x_1 ] 11.985225 s: APP: Syncing with 7 CPUs ... Done !!! [C7x_1 ] 11.985235 s: REMOTE_SERVICE: Init ... !!! [C7x_1 ] 11.985483 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 11.985502 s: VX_ZONE_INIT:Enabled [C7x_1 ] 11.985513 s: VX_ZONE_ERROR:Enabled [C7x_1 ] 11.985523 s: VX_ZONE_WARNING:Enabled [C7x_1 ] 11.985841 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C7x_1 ] 11.985856 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 11.985936 s: APP: OpenVX Target kernel init ... Done !!! [C7x_1 ] 11.985949 s: APP: Init ... Done !!! [C7x_1 ] 11.985958 s: APP: Run ... !!! [C7x_1 ] 11.985965 s: IPC: Starting echo test ... [C7x_1 ] 11.986629 s: APP: Run ... Done !!! [C7x_1 ] 11.990766 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s] [C7x_1 ] 11.990959 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s] [C7x_1 ] 11.992426 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[s] [C7x_1 ] 11.992571 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
ok, this seems now failing in allocating copy channel for UDMA copy operation.
Let me check it on EVM and share you the exact changes required to move VPAC to mcu2_1 and DMPAC to mcu2_0.
Regards,
Brijesh
Hi,
Can you please follow below steps to move VPAC to mcu2_1 and DMPAC to mcu2_0
With the above changes, you might see CQ Ring alloc failure on mcu2_1. but lets first check if above works fine.
Regards,
Brijesh
hi
Please verify if the content of the patch changes the host_id to TISCI_HOST_ID_MAIN_0_R5_5.
cfs-file/__key/communityserver-discussions-components-files/791/VHWA_5F00_Core_5F00_Moved.patch
please check this link i can't connect this link
thank you
the contents of the file "/cfs-file/__key/communityserver-discussions-components-files/791/VHWA_5F00_Core_5F00_Moved.patch" have been modified to change TISCI_HOST_ID_MAIN_0_R5_5 to TISCI_HOST_ID_MAIN_0_R5_2.
Although the contents of the "vision_app patch" cannot be viewed, the contents of the "app_cfg_mcu2_0.h" file have been modified as follows.
#undef ENABLE_VHWA_VPAC
#define ENABLE_VHWA_DMPAC
#undef ENABLE_VHWA_CODEC
The "app_cfg_mcu2_1.h" file has been modified as follows.
#define ENABLE_VHWA_VPAC
#undef ENABLE_VHWA_DMPAC
#define ENABLE_VHWA_CODEC
The result of the execution was as expected with a ring buffer error and the related log is attached.
[MCU2_0] 7.221143 s: CIO: Init ... Done !!!
[MCU2_0] 7.221214 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_0] 7.221253 s: APP: Init ... !!!
[MCU2_0] 7.221270 s: SCICLIENT: Init ... !!!
[MCU2_0] 7.221446 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[MCU2_0] 7.221484 s: SCICLIENT: DMSC FW revision 0x14
[MCU2_0] 7.221506 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0] 7.221529 s: SCICLIENT: Init ... Done !!!
[MCU2_0] 7.221548 s: UDMA: Init ... !!!
[MCU2_0] 7.222453 s: UDMA: Init ... Done !!!
[MCU2_0] 7.222501 s: MEM: Init ... !!!
[MCU2_0] 7.222532 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!!
[MCU2_0] 7.222586 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!!
[MCU2_0] 7.222631 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 65536 bytes !!!
[MCU2_0] 7.222674 s: MEM: Init ... Done !!!
[MCU2_0] 7.222692 s: FVID2: Init ... !!!
[MCU2_0] 7.222741 s: FVID2: Init ... Done !!!
[MCU2_0] 7.222763 s: VHWA: DMPAC: Init ... !!!
[MCU2_0] 7.222780 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_0] 7.222872 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 7.222897 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_0] 7.222955 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 7.222979 s: VHWA: DOF Init ... !!!
[MCU2_0] 7.228021 s: VHWA: DOF Init ... Done !!!
[MCU2_0] 7.228069 s: VHWA: SDE Init ... !!!
[MCU2_0] 7.230109 s: VHWA: SDE Init ... Done !!!
[MCU2_0] 7.230153 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_0] 7.230177 s: IPC: Init ... !!!
[MCU2_0] 7.230205 s: IPC: 8 CPUs participating in IPC !!!
[MCU2_0] 7.237136 s: IPC: Init ... Done !!!
[MCU2_0] 7.237191 s: APP: Syncing with 7 CPUs ... !!!
[MCU2_1] 7.181656 s: CIO: Init ... Done !!!
[MCU2_1] 7.181727 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_1] 7.181768 s: APP: Init ... !!!
[MCU2_1] 7.181786 s: SCICLIENT: Init ... !!!
[MCU2_1] 7.181972 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[MCU2_1] 7.182009 s: SCICLIENT: DMSC FW revision 0x14
[MCU2_1] 7.182033 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1] 7.182056 s: SCICLIENT: Init ... Done !!!
[MCU2_1] 7.182077 s: UDMA: Init ... !!!
[MCU2_1] 7.183060 s: UDMA: Init ... Done !!!
[MCU2_1] 7.183109 s: MEM: Init ... !!!
[MCU2_1] 7.183142 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!!
[MCU2_1] 7.183192 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!!
[MCU2_1] 7.183236 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce010000 of size 67043328 bytes !!!
[MCU2_1] 7.183281 s: MEM: Init ... Done !!!
[MCU2_1] 7.183299 s: FVID2: Init ... !!!
[MCU2_1] 7.183349 s: FVID2: Init ... Done !!!
[MCU2_1] 7.183372 s: VHWA: VPAC Init ... !!!
[MCU2_1] 7.183390 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_1] 7.183487 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1] 7.183515 s: VHWA: LDC Init ... !!!
[MCU2_1] 7.186178 s: VHWA: LDC Init ... Done !!!
[MCU2_1] 7.186225 s: VHWA: MSC Init ... !!!
[MCU2_1] 7.196315 s: VHWA: MSC Init ... Done !!!
[MCU2_1] 7.196363 s: VHWA: NF Init ... !!!
[MCU2_1] 7.197777 s: VHWA: NF Init ... Done !!!
[MCU2_1] 7.197822 s: VHWA: VISS Init ... !!!
[MCU2_1] 7.199410 s: [UDMA]
[MCU2_1] 7.199448 s: [Error] CQ ring alloc failed!!!
[MCU2_1] 7.199485 s: [UDMA]
[MCU2_1] 7.199500 s: [Error] Channel resource allocation failed!!
[MCU3_0] 11.825657 s: CIO: Init ... Done !!!
[MCU3_0] 11.825728 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU3_0] 11.825771 s: APP: Init ... !!!
[MCU3_0] 11.825791 s: SCICLIENT: Init ... !!!
[MCU3_0] 11.825978 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[MCU3_0] 11.826017 s: SCICLIENT: DMSC FW revision 0x14
[MCU3_0] 11.826042 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_0] 11.826066 s: SCICLIENT: Init ... Done !!!
[MCU3_0] 11.826089 s: MEM: Init ... !!!
[MCU3_0] 11.826118 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3c00000 of size 2097152 bytes !!!
[MCU3_0] 11.826165 s: MEM: Init ... Done !!!
[MCU3_0] 11.826184 s: IPC: Init ... !!!
[MCU3_0] 11.826211 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_0] 11.833057 s: IPC: Init ... Done !!!
[MCU3_0] 11.833112 s: APP: Syncing with 7 CPUs ... !!!
[MCU3_1] 11.888650 s: CIO: Init ... Done !!!
[MCU3_1] 11.888724 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU3_1] 11.888768 s: APP: Init ... !!!
[MCU3_1] 11.888786 s: SCICLIENT: Init ... !!!
[MCU3_1] 11.888968 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[MCU3_1] 11.889006 s: SCICLIENT: DMSC FW revision 0x14
[MCU3_1] 11.889031 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_1] 11.889057 s: SCICLIENT: Init ... Done !!!
[MCU3_1] 11.889078 s: MEM: Init ... !!!
[MCU3_1] 11.889106 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3e00000 of size 2097152 bytes !!!
[MCU3_1] 11.889154 s: MEM: Init ... Done !!!
[MCU3_1] 11.889174 s: IPC: Init ... !!!
[MCU3_1] 11.889202 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_1] 11.896093 s: IPC: Init ... Done !!!
[MCU3_1] 11.896149 s: APP: Syncing with 7 CPUs ... !!!
[C6x_1 ] 11.967508 s: CIO: Init ... Done !!!
[C6x_1 ] 11.967540 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
[C6x_1 ] 11.967553 s: APP: Init ... !!!
[C6x_1 ] 11.967561 s: SCICLIENT: Init ... !!!
[C6x_1 ] 11.967730 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[C6x_1 ] 11.967741 s: SCICLIENT: DMSC FW revision 0x14
[C6x_1 ] 11.967750 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ] 11.967759 s: SCICLIENT: Init ... Done !!!
[C6x_1 ] 11.967769 s: UDMA: Init ... !!!
[C6x_1 ] 11.968799 s: UDMA: Init ... Done !!!
[C6x_1 ] 11.968820 s: MEM: Init ... !!!
[C6x_1 ] 11.968832 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!!
[C6x_1 ] 11.968849 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ] 11.968864 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!!
[C6x_1 ] 11.968880 s: MEM: Init ... Done !!!
[C6x_1 ] 11.968888 s: IPC: Init ... !!!
[C6x_1 ] 11.968900 s: IPC: 8 CPUs participating in IPC !!!
[C6x_1 ] 11.972573 s: IPC: Init ... Done !!!
[C6x_1 ] 11.972601 s: APP: Syncing with 7 CPUs ... !!!
[C6x_2 ] 12.036590 s: CIO: Init ... Done !!!
[C6x_2 ] 12.036622 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
[C6x_2 ] 12.036635 s: APP: Init ... !!!
[C6x_2 ] 12.036642 s: SCICLIENT: Init ... !!!
[C6x_2 ] 12.036810 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[C6x_2 ] 12.036822 s: SCICLIENT: DMSC FW revision 0x14
[C6x_2 ] 12.036830 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ] 12.036840 s: SCICLIENT: Init ... Done !!!
[C6x_2 ] 12.036849 s: UDMA: Init ... !!!
[C6x_2 ] 12.037892 s: UDMA: Init ... Done !!!
[C6x_2 ] 12.037913 s: MEM: Init ... !!!
[C6x_2 ] 12.037925 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!!
[C6x_2 ] 12.037942 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ] 12.037957 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!!
[C6x_2 ] 12.037973 s: MEM: Init ... Done !!!
[C6x_2 ] 12.037980 s: IPC: Init ... !!!
[C6x_2 ] 12.037993 s: IPC: 8 CPUs participating in IPC !!!
[C6x_2 ] 12.041681 s: IPC: Init ... Done !!!
[C6x_2 ] 12.041710 s: APP: Syncing with 7 CPUs ... !!!
[C7x_1 ] 12.112296 s: CIO: Init ... Done !!!
[C7x_1 ] 12.112317 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[C7x_1 ] 12.112333 s: APP: Init ... !!!
[C7x_1 ] 12.112341 s: SCICLIENT: Init ... !!!
[C7x_1 ] 12.112498 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[C7x_1 ] 12.112512 s: SCICLIENT: DMSC FW revision 0x14
[C7x_1 ] 12.112522 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ] 12.112532 s: SCICLIENT: Init ... Done !!!
[C7x_1 ] 12.112541 s: UDMA: Init ... !!!
[C7x_1 ] 12.112949 s: UDMA: Init ... Done !!!
[C7x_1 ] 12.112958 s: MEM: Init ... !!!
[C7x_1 ] 12.112969 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!!
[C7x_1 ] 12.112989 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
[C7x_1 ] 12.113006 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!!
[C7x_1 ] 12.113023 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ] 12.113040 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 234881024 bytes !!!
[C7x_1 ] 12.113058 s: MEM: Init ... Done !!!
[C7x_1 ] 12.113066 s: IPC: Init ... !!!
[C7x_1 ] 12.113076 s: IPC: 8 CPUs participating in IPC !!!
[C7x_1 ] 12.115159 s: IPC: Init ... Done !!!
[C7x_1 ] 12.115172 s: APP: Syncing with 7 CPUs ... !!!
ok, I will share one more patch by today to reduce number of rings for VPAC.
Regards,
Brijesh
Hi,
Can you please apply attached patch on PDK folder and try it out? This patch reduces the number of CQ rings in the VHWA driver and should help in above error.
Regards,
Brijesh
[MCU2_0] 7.711350 s: CIO: Init ... Done !!! [MCU2_0] 7.711421 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_0] 7.711459 s: APP: Init ... !!! [MCU2_0] 7.711476 s: SCICLIENT: Init ... !!! [MCU2_0] 7.711653 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU2_0] 7.711688 s: SCICLIENT: DMSC FW revision 0x14 [MCU2_0] 7.711711 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_0] 7.711733 s: SCICLIENT: Init ... Done !!! [MCU2_0] 7.711753 s: UDMA: Init ... !!! [MCU2_0] 7.712661 s: UDMA: Init ... Done !!! [MCU2_0] 7.712707 s: MEM: Init ... !!! [MCU2_0] 7.712736 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!! [MCU2_0] 7.712792 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!! [MCU2_0] 7.712841 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 65536 bytes !!! [MCU2_0] 7.712884 s: MEM: Init ... Done !!! [MCU2_0] 7.712902 s: IPC: Init ... !!! [MCU2_0] 7.712929 s: IPC: 8 CPUs participating in IPC !!! [MCU2_0] 7.719844 s: IPC: Init ... Done !!! [MCU2_0] 7.719900 s: APP: Syncing with 7 CPUs ... !!! [MCU2_0] 12.874272 s: APP: Syncing with 7 CPUs ... Done !!! [MCU2_0] 12.874444 s: REMOTE_SERVICE: Init ... !!! [MCU2_0] 12.875953 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_0] 12.876015 s: ETHFW: Init ... !!! [MCU2_0] 12.881838 s: CPSW_9G Test on MAIN NAVSS [MCU2_0] 12.895271 s: ETHFW: Version : 0.01.01 [MCU2_0] 12.895333 s: ETHFW: Build Date: Feb 8, 2023 [MCU2_0] 12.895358 s: ETHFW: Build Time: 14:59:12 [MCU2_0] 12.895378 s: ETHFW: Commit SHA: e7b944fe [MCU2_0] 12.895403 s: ETHFW: Init ... DONE !!! [MCU2_0] 12.895446 s: ETHFW: Remove server Init ... !!! [MCU2_0] 12.896612 s: Remote demo device (core : mcu2_0) ..... [MCU2_0] 12.896675 s: ETHFW: Remove server Init ... DONE !!! [MCU2_0] 12.902187 s: Host MAC address: 70:ff:76:1d:92:c2 [MCU2_0] 12.946448 s: APP: Setup Dual Vout !!! [MCU2_1] 7.671584 s: CIO: Init ... Done !!! [MCU2_1] 7.671652 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_1] 7.671691 s: APP: Init ... !!! [MCU2_1] 7.671708 s: SCICLIENT: Init ... !!! [MCU2_1] 7.671893 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU2_1] 7.671929 s: SCICLIENT: DMSC FW revision 0x14 [MCU2_1] 7.671952 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_1] 7.671974 s: SCICLIENT: Init ... Done !!! [MCU2_1] 7.671994 s: UDMA: Init ... !!! [MCU2_1] 7.672974 s: UDMA: Init ... Done !!! [MCU2_1] 7.673022 s: MEM: Init ... !!! [MCU2_1] 7.673056 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!! [MCU2_1] 7.673108 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!! [MCU2_1] 7.673154 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce010000 of size 67043328 bytes !!! [MCU2_1] 7.673198 s: MEM: Init ... Done !!! [MCU2_1] 7.673216 s: IPC: Init ... !!! [MCU2_1] 7.673244 s: IPC: 8 CPUs participating in IPC !!! [MCU2_1] 7.680148 s: IPC: Init ... Done !!! [MCU2_1] 7.680205 s: APP: Syncing with 7 CPUs ... !!! [MCU2_1] 12.874271 s: APP: Syncing with 7 CPUs ... Done !!! [MCU2_1] 12.874308 s: REMOTE_SERVICE: Init ... !!! [MCU2_1] 12.875835 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_1] 12.875894 s: FVID2: Init ... !!! [MCU2_1] 12.875964 s: FVID2: Init ... Done !!! [MCU2_1] 12.875989 s: VHWA: VPAC Init ... !!! [MCU2_1] 12.876007 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2 [MCU2_1] 12.876109 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 12.876136 s: VHWA: LDC Init ... !!! [MCU2_1] 12.879913 s: VHWA: LDC Init ... Done !!! [MCU2_1] 12.879969 s: VHWA: MSC Init ... !!! [MCU2_1] 12.890496 s: VHWA: MSC Init ... Done !!! [MCU2_1] 12.890548 s: VHWA: NF Init ... !!! [MCU2_1] 12.891955 s: VHWA: NF Init ... Done !!! [MCU2_1] 12.891996 s: VHWA: VISS Init ... !!! [MCU2_1] 12.896682 s: VHWA: VISS Init ... Done !!! [MCU2_1] 12.896734 s: VHWA: VPAC Init ... Done !!! [MCU2_1] 12.896758 s: VHWA: Codec: Init ... !!! [MCU2_1] 12.896776 s: VHWA: VDEC Init ... !!! [MCU2_1] 12.909708 s: VHWA: VDEC Init ... Done !!! [MCU2_1] 12.909760 s: VHWA: VENC Init ... !!! [MCU2_1] 12.951749 s: VHWA: VENC Init ... Done !!! [MCU2_1] 12.909878 s: MM_ENC_Init: No OCM RAM pool available, fallback to DDR mode for above mp params [MCU2_1] 12.951800 s: VHWA: Init ... Done !!! [MCU2_1] 12.951835 s: VX_ZONE_INIT:Enabled [MCU2_1] 12.951859 s: VX_ZONE_ERROR:Enabled [MCU2_1] 12.951877 s: VX_ZONE_WARNING:Enabled [MCU2_1] 12.952867 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_NF [MCU2_1] 12.953095 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_LDC1 [MCU2_1] 12.953319 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_MSC1 [MCU2_1] 12.953579 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_MSC2 [MCU2_1] 12.953832 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_VISS1 [MCU2_1] 12.954050 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VDEC1 [MCU2_1] 12.954263 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VDEC2 [MCU2_1] 12.954527 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VENC1 [MCU2_1] 12.954763 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VENC2 [MCU2_1] 12.955003 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_CE_VISS [MCU2_1] 12.957622 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_CE_RC [MCU2_1] 12.957669 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [MCU2_1] 12.957697 s: APP: OpenVX Target kernel init ... !!! [MCU2_1] 13.003944 s: [TWEAK_STUB.INIT] Tweak is not compiled-in [MCU2_1] 13.004001 s: [STORAGE_TRACE.INIT] Trace is not compiled-in [MCU2_1] 13.004568 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_1] 13.004613 s: UDMA Copy: Init ... !!! [MCU2_1] 13.004717 s: [UDMA] [MCU2_1] 13.004743 s: [Error] RM Alloc Blkcpy Ch failed!!! [MCU2_1] 13.004775 s: [UDMA] [MCU2_1] 13.004789 s: [Error] Channel resource allocation failed!! [MCU2_1] 13.004812 s: UDMA : ERROR: UDMA channel open failed!! [MCU2_1] 13.004863 s: UDMA : ERROR: Default channel object create failed!!! [MCU2_1] 13.004893 s: UDMA Copy: Init ... Done !!! [MCU3_0] 12.583686 s: CIO: Init ... Done !!! [MCU3_0] 12.583761 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU3_0] 12.583808 s: APP: Init ... !!! [MCU3_0] 12.583830 s: SCICLIENT: Init ... !!! [MCU3_0] 12.584021 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU3_0] 12.584060 s: SCICLIENT: DMSC FW revision 0x14 [MCU3_0] 12.584084 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU3_0] 12.584109 s: SCICLIENT: Init ... Done !!! [MCU3_0] 12.584130 s: MEM: Init ... !!! [MCU3_0] 12.584158 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3c00000 of size 2097152 bytes !!! [MCU3_0] 12.584158 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3c00000 of size 2097152 bytes !!! [MCU3_0] 12.584207 s: MEM: Init ... Done !!! [MCU3_0] 12.584226 s: IPC: Init ... !!! [MCU3_0] 12.584226 s: IPC: Init ... !!! [MCU3_0] 12.584254 s: IPC: 8 CPUs participating in IPC !!! [MCU3_0] 12.591172 s: IPC: Init ... Done !!! [MCU3_0] 12.591172 s: IPC: Init ... Done !!! [MCU3_0] 12.591227 s: APP: Syncing with 7 CPUs ... !!! [MCU3_0] 12.591227 s: APP: Syncing with 7 CPUs ... !!! [MCU3_0] 12.874271 s: APP: Syncing with 7 CPUs ... Done !!! [MCU3_0] 12.874271 s: APP: Syncing with 7 CPUs ... Done !!! [MCU3_0] 12.874309 s: REMOTE_SERVICE: Init ... !!! [MCU3_0] 12.875833 s: REMOTE_SERVICE: Init ... Done !!! [MCU3_0] 12.875895 s: APP: Init ... Done !!! [MCU3_0] 12.875925 s: APP: Run ... !!! [MCU3_0] 12.875947 s: IPC: Starting echo test ... [MCU3_0] 12.878958 s: APP: Run ... Done !!! [MCU3_0] 12.879863 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_0] 12.880052 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_0] 12.881685 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[x] C7X_1[P] [MCU3_0] 12.882164 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] [MCU3_1] 12.646698 s: CIO: Init ... Done !!! [MCU3_1] 12.646772 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU3_1] 12.646815 s: APP: Init ... !!! [MCU3_1] 12.646834 s: SCICLIENT: Init ... !!! [MCU3_1] 12.647018 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU3_1] 12.647057 s: SCICLIENT: DMSC FW revision 0x14 [MCU3_1] 12.647084 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU3_1] 12.647108 s: SCICLIENT: Init ... Done !!! [MCU3_1] 12.647131 s: MEM: Init ... !!! [MCU3_1] 12.647161 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3e00000 of size 2097152 bytes !!! [MCU3_1] 12.647210 s: MEM: Init ... Done !!! [MCU3_1] 12.647229 s: IPC: Init ... !!! [MCU3_1] 12.647257 s: IPC: 8 CPUs participating in IPC !!! [MCU3_1] 12.654204 s: IPC: Init ... Done !!! [MCU3_1] 12.654264 s: APP: Syncing with 7 CPUs ... !!! [MCU3_1] 12.874272 s: APP: Syncing with 7 CPUs ... Done !!! [MCU3_1] 12.874310 s: REMOTE_SERVICE: Init ... !!! [MCU3_1] 12.875809 s: REMOTE_SERVICE: Init ... Done !!! [MCU3_1] 12.875870 s: APP: Init ... Done !!! [MCU3_1] 12.875900 s: APP: Run ... !!! [MCU3_1] 12.875921 s: IPC: Starting echo test ... [MCU3_1] 12.878899 s: APP: Run ... Done !!! [MCU3_1] 12.879693 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_1] 12.880080 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_1] 12.881582 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[x] C7X_1[P] [MCU3_1] 12.882079 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [C6x_1 ] 12.725349 s: CIO: Init ... Done !!! [C6x_1 ] 12.725381 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_1 ] 12.725394 s: APP: Init ... !!! [C6x_1 ] 12.725401 s: SCICLIENT: Init ... !!! [C6x_1 ] 12.725569 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C6x_1 ] 12.725581 s: SCICLIENT: DMSC FW revision 0x14 [C6x_1 ] 12.725590 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_1 ] 12.725599 s: SCICLIENT: Init ... Done !!! [C6x_1 ] 12.725608 s: UDMA: Init ... !!! [C6x_1 ] 12.726644 s: UDMA: Init ... Done !!! [C6x_1 ] 12.726665 s: MEM: Init ... !!! [C6x_1 ] 12.726676 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!! [C6x_1 ] 12.726693 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_1 ] 12.726708 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!! [C6x_1 ] 12.726724 s: MEM: Init ... Done !!! [C6x_1 ] 12.726732 s: IPC: Init ... !!! [C6x_1 ] 12.726744 s: IPC: 8 CPUs participating in IPC !!! [C6x_1 ] 12.730423 s: IPC: Init ... Done !!! [C6x_1 ] 12.730452 s: APP: Syncing with 7 CPUs ... !!! [C6x_1 ] 12.874269 s: APP: Syncing with 7 CPUs ... Done !!! [C6x_1 ] 12.874279 s: REMOTE_SERVICE: Init ... !!! [C6x_1 ] 12.874943 s: REMOTE_SERVICE: Init ... Done !!! [C6x_1 ] 12.874988 s: VX_ZONE_INIT:Enabled [C6x_1 ] 12.874999 s: VX_ZONE_ERROR:Enabled [C6x_1 ] 12.875009 s: VX_ZONE_WARNING:Enabled [C6x_1 ] 12.875913 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_1 ] 12.875932 s: APP: OpenVX Target kernel init ... !!! [C6x_1 ] 12.876221 s: APP: OpenVX Target kernel init ... Done !!! [C6x_1 ] 12.876241 s: UDMA Copy: Init ... !!! [C6x_1 ] 12.879306 s: UDMA Copy: Init ... Done !!! [C6x_1 ] 12.879330 s: APP: Init ... Done !!! [C6x_1 ] 12.879584 s: APP: Run ... !!! [C6x_1 ] 12.879595 s: IPC: Starting echo test ... [C6x_1 ] 12.881086 s: APP: Run ... Done !!! [C6x_1 ] 12.881622 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[x] C7X_1[P] [C6x_1 ] 12.881692 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[x] C7X_1[P] [C6x_1 ] 12.881764 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[.] C7X_1[P] [C6x_1 ] 12.881995 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_2 ] 12.794545 s: CIO: Init ... Done !!! [C6x_2 ] 12.794578 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_2 ] 12.794592 s: APP: Init ... !!! [C6x_2 ] 12.794599 s: SCICLIENT: Init ... !!! [C6x_2 ] 12.794772 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C6x_2 ] 12.794783 s: SCICLIENT: DMSC FW revision 0x14 [C6x_2 ] 12.794792 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_2 ] 12.794802 s: SCICLIENT: Init ... Done !!! [C6x_2 ] 12.794812 s: UDMA: Init ... !!! [C6x_2 ] 12.795851 s: UDMA: Init ... Done !!! [C6x_2 ] 12.795872 s: MEM: Init ... !!! [C6x_2 ] 12.795884 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!! [C6x_2 ] 12.795901 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_2 ] 12.795916 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!! [C6x_2 ] 12.795932 s: MEM: Init ... Done !!! [C6x_2 ] 12.795940 s: IPC: Init ... !!! [C6x_2 ] 12.795952 s: IPC: 8 CPUs participating in IPC !!! [C6x_2 ] 12.799675 s: IPC: Init ... Done !!! [C6x_2 ] 12.799704 s: APP: Syncing with 7 CPUs ... !!! [C6x_2 ] 12.874269 s: APP: Syncing with 7 CPUs ... Done !!! [C6x_2 ] 12.874280 s: REMOTE_SERVICE: Init ... !!! [C6x_2 ] 12.874942 s: REMOTE_SERVICE: Init ... Done !!! [C6x_2 ] 12.874988 s: VX_ZONE_INIT:Enabled [C6x_2 ] 12.874999 s: VX_ZONE_ERROR:Enabled [C6x_2 ] 12.875009 s: VX_ZONE_WARNING:Enabled [C6x_2 ] 12.875906 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_2 ] 12.875923 s: APP: OpenVX Target kernel init ... !!! [C6x_2 ] 12.876220 s: APP: OpenVX Target kernel init ... Done !!! [C6x_2 ] 12.876241 s: UDMA Copy: Init ... !!! [C6x_2 ] 12.879415 s: UDMA Copy: Init ... Done !!! [C6x_2 ] 12.879438 s: APP: Init ... Done !!! [C6x_2 ] 12.879934 s: APP: Run ... !!! [C6x_2 ] 12.879943 s: IPC: Starting echo test ... [C6x_2 ] 12.881529 s: APP: Run ... Done !!! [C6x_2 ] 12.882108 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[.] C66X_2[s] C7X_1[P] [C6x_2 ] 12.882167 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 12.882219 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 12.882250 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C7x_1 ] 12.871358 s: CIO: Init ... Done !!! [C7x_1 ] 12.871382 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [C7x_1 ] 12.871398 s: APP: Init ... !!! [C7x_1 ] 12.871405 s: SCICLIENT: Init ... !!! [C7x_1 ] 12.871560 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C7x_1 ] 12.871574 s: SCICLIENT: DMSC FW revision 0x14 [C7x_1 ] 12.871584 s: SCICLIENT: DMSC FW ABI revision 3.1 [C7x_1 ] 12.871595 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 12.871603 s: UDMA: Init ... !!! [C7x_1 ] 12.872012 s: UDMA: Init ... Done !!! [C7x_1 ] 12.872022 s: MEM: Init ... !!! [C7x_1 ] 12.872032 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!! [C7x_1 ] 12.872053 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!! [C7x_1 ] 12.872071 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!! [C7x_1 ] 12.872088 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!! [C7x_1 ] 12.872104 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 234881024 bytes !!! [C7x_1 ] 12.872122 s: MEM: Init ... Done !!! [C7x_1 ] 12.872130 s: IPC: Init ... !!! [C7x_1 ] 12.872139 s: IPC: 8 CPUs participating in IPC !!! [C7x_1 ] 12.874243 s: IPC: Init ... Done !!! [C7x_1 ] 12.874256 s: APP: Syncing with 7 CPUs ... !!! [C7x_1 ] 12.874270 s: APP: Syncing with 7 CPUs ... Done !!! [C7x_1 ] 12.874281 s: REMOTE_SERVICE: Init ... !!! [C7x_1 ] 12.874533 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 12.874533 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 12.874553 s: VX_ZONE_INIT:Enabled [C7x_1 ] 12.874592 s: VX_ZONE_ERROR:Enabled [C7x_1 ] 12.874604 s: VX_ZONE_WARNING:Enabled [C7x_1 ] 12.874905 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C7x_1 ] 12.874919 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 12.874919 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 12.874995 s: APP: OpenVX Target kernel init ... Done !!! [C7x_1 ] 12.875008 s: APP: Init ... Done !!! [C7x_1 ] 12.875017 s: APP: Run ... !!! [C7x_1 ] 12.875025 s: IPC: Starting echo test ... [C7x_1 ] 12.875680 s: APP: Run ... Done !!! [C7x_1 ] 12.879645 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s] [C7x_1 ] 12.879709 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s] [C7x_1 ] 12.881512 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[x] C7X_1[s] [C7x_1 ] 12.881987 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
I have applied the patch you provided and the results are in the attached log.
I have a question about the patch content. The variable 'repeatCnt' is not declared, but it is being used in the patch content (I have commented out the code.). The modification of the vhwa_m2mVissPriv.h file seems strange. As a result, the ringbuffer error has not been resolved, and now there is an additional log "UDMA: ERROR: Default channel object create failed!!!" compared to before.
The parameters for the function Vhwa_m2mVissAllocUdmaMem are only Vhwa_M2mVissHandleObj *hObj, but in the patch there is Vhwa_M2mVissInstObj *instObj.
I kindly request you to re-check the patch you uploaded.
ps. i use psdkra 7.1
For the below error, please allocate additional block copy channels on mcu2_1..
[MCU2_1] 13.004613 s: UDMA Copy: Init ... !!!
[MCU2_1] 13.004717 s: [UDMA]
[MCU2_1] 13.004743 s: [Error] RM Alloc Blkcpy Ch failed!!!
[MCU2_1] 13.004775 s: [UDMA]
[MCU2_1] 13.004789 s: [Error] Channel resource allocation failed!!
[MCU2_1] 13.004812 s: UDMA : ERROR: UDMA channel open failed!!
[MCU2_1] 13.004863 s: UDMA : ERROR: Default channel object create failed!!!
Also before sharing patch, i did run multi-camera demo and it ran fine. So no issue in the patch..
Regards,
Brijesh
I'm sorry, I made a mistake. Could you please tell me about assigning additional copy channels in mcu2_1?
Can you please follow below FAQ and allocate block copy channels for mcu2_1?
Regards,
Brijesh
As mentioned, I tried to adjust the channels block copy count by adjusting the normal capacity rx channel count and normal capacity tx channel count, but the value of rx channel count in MAIN_R5_2 (MCU2_1) was set to 1, so I also had to adjust the normal capacity rtx channel count in MCU2_0. I don't know the exact values of how much to adjust and allocate, so I swapped the setting values of MCU2_0 and MCU2_1.
As a result, I allocated the following values to
MCU2_0: normal capacity rx channel count = 1
normal capacity tx channel count = 6
normal capacity channels block copy count = 1
And to MCU2_1:
normal capacity rx channel count = 16
normal capacity tx channel count = 10
normal capacity channels block copy count = 4
The result appears to be that initialization does not occur normally. Please refer to the attached logs.
Would it be possible for you to provide a detailed explanation about adjusting the block channel count value?
[MCU2_0] 7.414398 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_0] 7.414437 s: APP: Init ... !!! [MCU2_0] 7.414454 s: SCICLIENT: Init ... !!! [MCU2_0] 7.414630 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU2_0] 7.414666 s: SCICLIENT: DMSC FW revision 0x14 [MCU2_0] 7.414688 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_0] 7.414711 s: SCICLIENT: Init ... Done !!! [MCU2_0] 7.414731 s: UDMA: Init ... !!! [MCU2_0] 7.415648 s: UDMA: Init ... Done !!! [MCU2_0] 7.415696 s: MEM: Init ... !!! [MCU2_0] 7.415730 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!! [MCU2_0] 7.415786 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!! [MCU2_0] 7.415835 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 65536 bytes !!! [MCU2_0] 7.415878 s: MEM: Init ... Done !!! [MCU2_0] 7.415896 s: IPC: Init ... !!! [MCU2_0] 7.415923 s: IPC: 8 CPUs participating in IPC !!! [MCU2_0] 7.422946 s: IPC: Init ... Done !!! [MCU2_0] 7.423002 s: APP: Syncing with 7 CPUs ... !!! [MCU2_0] 12.405284 s: APP: Syncing with 7 CPUs ... Done !!! [MCU2_0] 12.405454 s: REMOTE_SERVICE: Init ... !!! [MCU2_0] 12.406935 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_0] 12.406997 s: ETHFW: Init ... !!! [MCU2_0] 12.412807 s: CPSW_9G Test on MAIN NAVSS [MCU2_1] 7.370841 s: CIO: Init ... Done !!! [MCU2_1] 7.370912 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_1] 7.370953 s: APP: Init ... !!! [MCU2_1] 7.370972 s: SCICLIENT: Init ... !!! [MCU2_1] 7.371159 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU2_1] 7.371194 s: SCICLIENT: DMSC FW revision 0x14 [MCU2_1] 7.371217 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_1] 7.371239 s: SCICLIENT: Init ... Done !!! [MCU2_1] 7.371260 s: UDMA: Init ... !!! [MCU2_1] 7.372253 s: UDMA: Init ... Done !!! [MCU2_1] 7.372304 s: MEM: Init ... !!! [MCU2_1] 7.372336 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!! [MCU2_1] 7.372385 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!! [MCU2_1] 7.372431 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce010000 of size 67043328 bytes !!! [MCU2_1] 7.372476 s: MEM: Init ... Done !!! [MCU2_1] 7.372496 s: IPC: Init ... !!! [MCU2_1] 7.372525 s: IPC: 8 CPUs participating in IPC !!! [MCU2_1] 7.379459 s: IPC: Init ... Done !!! [MCU2_1] 7.379516 s: APP: Syncing with 7 CPUs ... !!! [MCU2_1] 12.405282 s: APP: Syncing with 7 CPUs ... Done !!! [MCU2_1] 12.405317 s: REMOTE_SERVICE: Init ... !!! [MCU2_1] 12.406832 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_1] 12.406888 s: FVID2: Init ... !!! [MCU2_1] 12.406955 s: FVID2: Init ... Done !!! [MCU2_1] 12.406980 s: VHWA: VPAC Init ... !!! [MCU2_1] 12.406998 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2 [MCU2_1] 12.407109 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 12.407137 s: VHWA: LDC Init ... !!! [MCU2_1] 12.410880 s: VHWA: LDC Init ... Done !!! [MCU2_1] 12.410936 s: VHWA: MSC Init ... !!! [MCU2_1] 12.421495 s: VHWA: MSC Init ... Done !!! [MCU2_1] 12.421546 s: VHWA: NF Init ... !!! [MCU2_1] 12.422952 s: VHWA: NF Init ... Done !!! [MCU2_1] 12.422996 s: VHWA: VISS Init ... !!! [MCU3_0] 12.113669 s: CIO: Init ... Done !!! [MCU3_0] 12.113741 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU3_0] 12.113786 s: APP: Init ... !!! [MCU3_0] 12.113805 s: SCICLIENT: Init ... !!! [MCU3_0] 12.113992 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU3_0] 12.114030 s: SCICLIENT: DMSC FW revision 0x14 [MCU3_0] 12.114056 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU3_0] 12.114080 s: SCICLIENT: Init ... Done !!! [MCU3_0] 12.114101 s: MEM: Init ... !!! [MCU3_0] 12.114128 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3c00000 of size 2097152 bytes !!! [MCU3_0] 12.114179 s: MEM: Init ... Done !!! [MCU3_0] 12.114199 s: IPC: Init ... !!! [MCU3_0] 12.114227 s: IPC: 8 CPUs participating in IPC !!! [MCU3_0] 12.121109 s: IPC: Init ... Done !!! [MCU3_0] 12.121167 s: APP: Syncing with 7 CPUs ... !!! [MCU3_0] 12.405283 s: APP: Syncing with 7 CPUs ... Done !!! [MCU3_0] 12.405320 s: REMOTE_SERVICE: Init ... !!! [MCU3_0] 12.406801 s: REMOTE_SERVICE: Init ... Done !!! [MCU3_0] 12.406864 s: APP: Init ... Done !!! [MCU3_0] 12.406895 s: APP: Run ... !!! [MCU3_0] 12.406919 s: IPC: Starting echo test ... [MCU3_0] 12.409887 s: APP: Run ... Done !!! [MCU3_0] 12.410773 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_0] 12.410907 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_0] 12.412644 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[x] C66X_2[P] C7X_1[P] [MCU3_0] 12.413109 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P] [MCU3_1] 12.176679 s: CIO: Init ... Done !!! [MCU3_1] 12.176750 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU3_1] 12.176791 s: APP: Init ... !!! [MCU3_1] 12.176810 s: SCICLIENT: Init ... !!! [MCU3_1] 12.176994 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [MCU3_1] 12.177034 s: SCICLIENT: DMSC FW revision 0x14 [MCU3_1] 12.177062 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU3_1] 12.177089 s: SCICLIENT: Init ... Done !!! [MCU3_1] 12.177112 s: MEM: Init ... !!! [MCU3_1] 12.177141 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3e00000 of size 2097152 bytes !!! [MCU3_1] 12.177190 s: MEM: Init ... Done !!! [MCU3_1] 12.177209 s: IPC: Init ... !!! [MCU3_1] 12.177236 s: IPC: 8 CPUs participating in IPC !!! [MCU3_1] 12.184152 s: IPC: Init ... Done !!! [MCU3_1] 12.184211 s: APP: Syncing with 7 CPUs ... !!! [MCU3_1] 12.405284 s: APP: Syncing with 7 CPUs ... Done !!! [MCU3_1] 12.405321 s: REMOTE_SERVICE: Init ... !!! [MCU3_1] 12.406831 s: REMOTE_SERVICE: Init ... Done !!! [MCU3_1] 12.406891 s: APP: Init ... Done !!! [MCU3_1] 12.406915 s: APP: Run ... !!! [MCU3_1] 12.406937 s: IPC: Starting echo test ... [MCU3_1] 12.409936 s: APP: Run ... Done !!! [MCU3_1] 12.410846 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_1] 12.410948 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [MCU3_1] 12.412659 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[x] C66X_2[P] C7X_1[P] [MCU3_1] 12.413128 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [C6x_1 ] 12.255537 s: CIO: Init ... Done !!! [C6x_1 ] 12.255569 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_1 ] 12.255582 s: APP: Init ... !!! [C6x_1 ] 12.255589 s: SCICLIENT: Init ... !!! [C6x_1 ] 12.255761 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C6x_1 ] 12.255772 s: SCICLIENT: DMSC FW revision 0x14 [C6x_1 ] 12.255781 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_1 ] 12.255790 s: SCICLIENT: Init ... Done !!! [C6x_1 ] 12.255799 s: UDMA: Init ... !!! [C6x_1 ] 12.256836 s: UDMA: Init ... Done !!! [C6x_1 ] 12.256856 s: MEM: Init ... !!! [C6x_1 ] 12.256868 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!! [C6x_1 ] 12.256885 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_1 ] 12.256901 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!! [C6x_1 ] 12.256917 s: MEM: Init ... Done !!! [C6x_1 ] 12.256925 s: IPC: Init ... !!! [C6x_1 ] 12.256937 s: IPC: 8 CPUs participating in IPC !!! [C6x_1 ] 12.260623 s: IPC: Init ... Done !!! [C6x_1 ] 12.260652 s: APP: Syncing with 7 CPUs ... !!! [C6x_1 ] 12.405281 s: APP: Syncing with 7 CPUs ... Done !!! [C6x_1 ] 12.405292 s: REMOTE_SERVICE: Init ... !!! [C6x_1 ] 12.405951 s: REMOTE_SERVICE: Init ... Done !!! [C6x_1 ] 12.405996 s: VX_ZONE_INIT:Enabled [C6x_1 ] 12.406007 s: VX_ZONE_ERROR:Enabled [C6x_1 ] 12.406016 s: VX_ZONE_WARNING:Enabled [C6x_1 ] 12.406902 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_1 ] 12.406920 s: APP: OpenVX Target kernel init ... !!! [C6x_1 ] 12.407211 s: APP: OpenVX Target kernel init ... Done !!! [C6x_1 ] 12.407231 s: UDMA Copy: Init ... !!! [C6x_1 ] 12.410384 s: UDMA Copy: Init ... Done !!! [C6x_1 ] 12.410408 s: APP: Init ... Done !!! [C6x_1 ] 12.410899 s: APP: Run ... !!! [C6x_1 ] 12.410909 s: IPC: Starting echo test ... [C6x_1 ] 12.412493 s: APP: Run ... Done !!! [C6x_1 ] 12.413092 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[.] C7X_1[P] [C6x_1 ] 12.413130 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 12.413162 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 12.413192 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_2 ] 12.325668 s: CIO: Init ... Done !!! [C6x_2 ] 12.325701 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_2 ] 12.325715 s: APP: Init ... !!! [C6x_2 ] 12.325722 s: SCICLIENT: Init ... !!! [C6x_2 ] 12.325891 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C6x_2 ] 12.325903 s: SCICLIENT: DMSC FW revision 0x14 [C6x_2 ] 12.325912 s: SCICLIENT: DMSC FW ABI revision 3.1 [C6x_2 ] 12.325922 s: SCICLIENT: Init ... Done !!! [C6x_2 ] 12.325931 s: UDMA: Init ... !!! [C6x_2 ] 12.326973 s: UDMA: Init ... Done !!! [C6x_2 ] 12.326995 s: MEM: Init ... !!! [C6x_2 ] 12.327007 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!! [C6x_2 ] 12.327024 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_2 ] 12.327039 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!! [C6x_2 ] 12.327055 s: MEM: Init ... Done !!! [C6x_2 ] 12.327063 s: IPC: Init ... !!! [C6x_2 ] 12.327075 s: IPC: 8 CPUs participating in IPC !!! [C6x_2 ] 12.330774 s: IPC: Init ... Done !!! [C6x_2 ] 12.330803 s: APP: Syncing with 7 CPUs ... !!! [C6x_2 ] 12.405282 s: APP: Syncing with 7 CPUs ... Done !!! [C6x_2 ] 12.405293 s: REMOTE_SERVICE: Init ... !!! [C6x_2 ] 12.405953 s: REMOTE_SERVICE: Init ... Done !!! [C6x_2 ] 12.405998 s: VX_ZONE_INIT:Enabled [C6x_2 ] 12.406009 s: VX_ZONE_ERROR:Enabled [C6x_2 ] 12.406018 s: VX_ZONE_WARNING:Enabled [C6x_2 ] 12.406896 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C6x_2 ] 12.406914 s: APP: OpenVX Target kernel init ... !!! [C6x_2 ] 12.407209 s: APP: OpenVX Target kernel init ... Done !!! [C6x_2 ] 12.407230 s: UDMA Copy: Init ... !!! [C6x_2 ] 12.410278 s: UDMA Copy: Init ... Done !!! [C6x_2 ] 12.410301 s: APP: Init ... Done !!! [C6x_2 ] 12.410552 s: APP: Run ... !!! [C6x_2 ] 12.410562 s: IPC: Starting echo test ... [C6x_2 ] 12.412062 s: APP: Run ... Done !!! [C6x_2 ] 12.412606 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[x] C66X_2[s] C7X_1[P] [C6x_2 ] 12.412648 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[x] C66X_2[s] C7X_1[P] [C6x_2 ] 12.412678 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[x] C66X_2[s] C7X_1[P] [C6x_2 ] 12.412961 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C7x_1 ] 12.402392 s: CIO: Init ... Done !!! [C7x_1 ] 12.402413 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [C7x_1 ] 12.402428 s: APP: Init ... !!! [C7x_1 ] 12.402436 s: SCICLIENT: Init ... !!! [C7x_1 ] 12.402590 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr] [C7x_1 ] 12.402604 s: SCICLIENT: DMSC FW revision 0x14 [C7x_1 ] 12.402614 s: SCICLIENT: DMSC FW ABI revision 3.1 [C7x_1 ] 12.402625 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 12.402633 s: UDMA: Init ... !!! [C7x_1 ] 12.403039 s: UDMA: Init ... Done !!! [C7x_1 ] 12.403049 s: MEM: Init ... !!! [C7x_1 ] 12.403059 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!! [C7x_1 ] 12.403081 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!! [C7x_1 ] 12.403099 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!! [C7x_1 ] 12.403116 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!! [C7x_1 ] 12.403132 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 234881024 bytes !!! [C7x_1 ] 12.403150 s: MEM: Init ... Done !!! [C7x_1 ] 12.403158 s: IPC: Init ... !!! [C7x_1 ] 12.403169 s: IPC: 8 CPUs participating in IPC !!! [C7x_1 ] 12.405255 s: IPC: Init ... Done !!! [C7x_1 ] 12.405268 s: APP: Syncing with 7 CPUs ... !!! [C7x_1 ] 12.405282 s: APP: Syncing with 7 CPUs ... Done !!! [C7x_1 ] 12.405293 s: REMOTE_SERVICE: Init ... !!! [C7x_1 ] 12.405542 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 12.405562 s: VX_ZONE_INIT:Enabled [C7x_1 ] 12.405600 s: VX_ZONE_ERROR:Enabled [C7x_1 ] 12.405613 s: VX_ZONE_WARNING:Enabled [C7x_1 ] 12.405901 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!! [C7x_1 ] 12.405915 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 12.405993 s: APP: OpenVX Target kernel init ... Done !!! [C7x_1 ] 12.406006 s: APP: Init ... Done !!! [C7x_1 ] 12.406014 s: APP: Run ... !!! [C7x_1 ] 12.406022 s: IPC: Starting echo test ... [C7x_1 ] 12.406672 s: APP: Run ... Done !!! [C7x_1 ] 12.410604 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[x] C66X_2[x] C7X_1[s] [C7x_1 ] 12.410802 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s] [C7x_1 ] 12.412479 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[x] C66X_2[P] C7X_1[s] [C7x_1 ] 12.412951 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
I think it just needs one block copy channel. Can you get it from A72, without affecting mcu2_0?
Now it seems both mcu2_0 and mcu2_1 are stuck.
I would suggest getting one block copy or one TX+RX channel from A72 and assign it to mcu2_1..
One block copy channel is required for VISS. Because it uses this channel for GLBCE.
If you use memcpy for GLBCE, then we can avoid this block copy channel usage on mcu2_1, but it can potentially not give good performance.
Regards,
Brijesh
As you instructed, I reduced the RTX channel for A72 and increased the block copy channel for MCU2_1.
I am attaching the logs.
Could you please check if it is normal? Because the existing camera app is not running properly.
[MCU2_0] 7.247091 s: CIO: Init ... Done !!!
[MCU2_0] 7.247162 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_0] 7.247200 s: APP: Init ... !!!
[MCU2_0] 7.247219 s: SCICLIENT: Init ... !!!
[MCU2_0] 7.247401 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[MCU2_0] 7.247437 s: SCICLIENT: DMSC FW revision 0x14
[MCU2_0] 7.247459 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0] 7.247482 s: SCICLIENT: Init ... Done !!!
[MCU2_0] 7.247502 s: UDMA: Init ... !!!
[MCU2_0] 7.248424 s: UDMA: Init ... Done !!!
[MCU2_0] 7.248475 s: MEM: Init ... !!!
[MCU2_0] 7.248508 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!!
[MCU2_0] 7.248564 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!!
[MCU2_0] 7.248613 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 65536 bytes !!!
[MCU2_0] 7.248658 s: MEM: Init ... Done !!!
[MCU2_0] 7.248675 s: FVID2: Init ... !!!
[MCU2_0] 7.248722 s: FVID2: Init ... Done !!!
[MCU2_0] 7.248744 s: VHWA: DMPAC: Init ... !!!
[MCU2_0] 7.248763 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_0] 7.248852 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 7.248880 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_0] 7.248939 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 7.248963 s: VHWA: DOF Init ... !!!
[MCU2_0] 7.251754 s: VHWA: DOF Init ... Done !!!
[MCU2_0] 7.251801 s: VHWA: SDE Init ... !!!
[MCU2_0] 7.253219 s: VHWA: SDE Init ... Done !!!
[MCU2_0] 7.253268 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_0] 7.253293 s: IPC: Init ... !!!
[MCU2_0] 7.253322 s: IPC: 8 CPUs participating in IPC !!!
[MCU2_0] 7.260347 s: IPC: Init ... Done !!!
[MCU2_0] 7.260405 s: APP: Syncing with 7 CPUs ... !!!
[MCU2_0] 12.143920 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU2_0] 12.144085 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0] 12.145617 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0] 12.145682 s: ETHFW: Init ... !!!
[MCU2_0] 12.150612 s: CPSW_9G Test on MAIN NAVSS
[MCU2_0] 12.163927 s: ETHFW: Version : 0.01.01
[MCU2_0] 12.163990 s: ETHFW: Build Date: Feb 10, 2023
[MCU2_0] 12.164017 s: ETHFW: Build Time: 16:45:24
[MCU2_0] 12.164039 s: ETHFW: Commit SHA: e7b944fe
[MCU2_0] 12.164065 s: ETHFW: Init ... DONE !!!
[MCU2_0] 12.164089 s: ETHFW: Remove server Init ... !!!
[MCU2_0] 12.165342 s: Remote demo device (core : mcu2_0) .....
[MCU2_0] 12.165404 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0] 12.171016 s: Host MAC address: 70:ff:76:1d:92:c2
[MCU2_0] 12.215187 s: APP: Setup Dual Vout !!!
[MCU2_0] 12.257280 s: APP: Setup Dual Vout (0)... !!!
[MCU2_0] 12.343298 s: [Log] DssDsiI2c Initialize
[MCU2_0] 12.443336 s: I2c Varify d Error Address = 29, Value = 0
[MCU2_0] 12.543338 s: I2c Varify d Error Address = 33, Value = 0
[MCU2_0] 12.826342 s: I2c Varify d Error Address = 7054, Value = 0
[MCU2_0] 13.085897 s: I2c Varify d Error Address = 7a14, Value = 0
[MCU2_0] 13.340336 s: I2c Varify d Error Address = 6420, Value = 0
[MCU2_0] 13.595601 s: I2c Varify d Error Address = 6420, Value = 0
[MCU2_0] 13.681302 s: [Log] DssDsiI2c Initialize max96717
[MCU2_0] 13.882339 s: I2c Varify d Error Address = 10, Value = 11
[MCU2_0] 13.968299 s: [INFO] DssDsiI2c Initialize max9295D
[MCU2_0] 14.077709 s: I2c Varify d Error Address = 10, Value = 1
[MCU2_0] 14.077782 s: Serializer Done
[MCU2_0] 14.077816 s: VX_ZONE_INIT:Enabled
[MCU2_0] 14.077840 s: VX_ZONE_ERROR:Enabled
[MCU2_0] 14.077858 s: VX_ZONE_WARNING:Enabled
[MCU2_0] 14.078908 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target IPU1-0
[MCU2_0] 14.079216 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target DMPAC_SDE
[MCU2_0] 14.079493 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target DMPAC_DOF
[MCU2_0] 14.079788 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE1
[MCU2_0] 14.080075 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE2
[MCU2_0] 14.080409 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target DISPLAY1
[MCU2_0] 14.080702 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target DISPLAY2
[MCU2_0] 14.080966 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CSITX
[MCU2_0] 14.081292 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE3
[MCU2_0] 14.081589 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE4
[MCU2_0] 14.081875 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE5
[MCU2_0] 14.082202 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE6
[MCU2_0] 14.082506 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE7
[MCU2_0] 14.082788 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target CAPTURE8
[MCU2_0] 14.082842 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[MCU2_0] 14.082872 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0] 14.083252 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0] 14.083297 s: CSI2RX: Init ... !!!
[MCU2_0] 14.083317 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0] 14.083392 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 14.083421 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0] 14.083488 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 14.083514 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0] 14.083577 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 14.083601 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0] 14.083650 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 14.083675 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0] 14.083724 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 14.084384 s: CSI2RX: Init ... Done !!!
[MCU2_0] 14.084436 s: CSI2TX: Init ... !!!
[MCU2_0] 14.084458 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0] 14.084517 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 14.084545 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0] 14.084612 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 14.084636 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0] 14.084689 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 14.085202 s: CSI2TX: Init ... Done !!!
[MCU2_0] 14.085249 s: ISS: Init ... !!!
[MCU2_0] 14.085308 s: Found sensor OX01D10 at location 0
[MCU2_0] 14.085339 s: IssSensor_Init ... Done !!!
[MCU2_0] 14.085403 s: vissRemoteServer_Init ... Done !!!
[MCU2_0] 14.085453 s: IttRemoteServer_Init ... Done !!!
[MCU2_0] 14.085478 s: UDMA Copy: Init ... !!!
[MCU2_0] 14.086819 s: UDMA Copy: Init ... Done !!!
[MCU2_0] 14.086870 s: APP: Init ... Done !!!
[MCU2_0] 14.086894 s: APP: Run ... !!!
[MCU2_0] 14.086913 s: IPC: Starting echo test ...
[MCU2_0] 14.090041 s: APP: Run ... Done !!!
[MCU2_0] 14.091863 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.]
[MCU2_0] 14.092198 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[P]
[MCU2_0] 14.092409 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[P]
[MCU2_0] 14.092538 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[P]
[MCU2_0] 14.092653 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[P]
[MCU2_0] 14.092769 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU2_1] 7.205264 s: CIO: Init ... Done !!!
[MCU2_1] 7.205332 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_1] 7.205369 s: APP: Init ... !!!
[MCU2_1] 7.205386 s: SCICLIENT: Init ... !!!
[MCU2_1] 7.205571 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[MCU2_1] 7.205607 s: SCICLIENT: DMSC FW revision 0x14
[MCU2_1] 7.205631 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1] 7.205656 s: SCICLIENT: Init ... Done !!!
[MCU2_1] 7.205677 s: UDMA: Init ... !!!
[MCU2_1] 7.206667 s: UDMA: Init ... Done !!!
[MCU2_1] 7.206715 s: MEM: Init ... !!!
[MCU2_1] 7.206750 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!!
[MCU2_1] 7.206799 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!!
[MCU2_1] 7.206846 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce010000 of size 67043328 bytes !!!
[MCU2_1] 7.206891 s: MEM: Init ... Done !!!
[MCU2_1] 7.206909 s: FVID2: Init ... !!!
[MCU2_1] 7.206961 s: FVID2: Init ... Done !!!
[MCU2_1] 7.206986 s: VHWA: VPAC Init ... !!!
[MCU2_1] 7.207007 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_1] 7.207099 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1] 7.207127 s: VHWA: LDC Init ... !!!
[MCU2_1] 7.208866 s: VHWA: LDC Init ... Done !!!
[MCU2_1] 7.208913 s: VHWA: MSC Init ... !!!
[MCU2_1] 7.218982 s: VHWA: MSC Init ... Done !!!
[MCU2_1] 7.219028 s: VHWA: NF Init ... !!!
[MCU2_1] 7.220455 s: VHWA: NF Init ... Done !!!
[MCU2_1] 7.220501 s: VHWA: VISS Init ... !!!
[MCU2_1] 7.224754 s: VHWA: VISS Init ... Done !!!
[MCU2_1] 7.224805 s: VHWA: VPAC Init ... Done !!!
[MCU2_1] 7.224829 s: VHWA: Codec: Init ... !!!
[MCU2_1] 7.224848 s: VHWA: VDEC Init ... !!!
[MCU2_1] 7.238877 s: VHWA: VDEC Init ... Done !!!
[MCU2_1] 7.238930 s: VHWA: VENC Init ... !!!
[MCU2_1] 7.239043 s: MM_ENC_Init: No OCM RAM pool available, fallback to DDR mode for above mp params
[MCU2_1] 7.281536 s: VHWA: VENC Init ... Done !!!
[MCU2_1] 7.281589 s: VHWA: Init ... Done !!!
[MCU2_1] 7.281613 s: IPC: Init ... !!!
[MCU2_1] 7.281641 s: IPC: 8 CPUs participating in IPC !!!
[MCU2_1] 7.288530 s: IPC: Init ... Done !!!
[MCU2_1] 7.288584 s: APP: Syncing with 7 CPUs ... !!!
[MCU2_1] 12.143918 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU2_1] 12.143955 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1] 12.145524 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1] 12.145596 s: VX_ZONE_INIT:Enabled
[MCU2_1] 12.145623 s: VX_ZONE_ERROR:Enabled
[MCU2_1] 12.145642 s: VX_ZONE_WARNING:Enabled
[MCU2_1] 12.146728 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_NF
[MCU2_1] 12.146990 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_LDC1
[MCU2_1] 12.147282 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_MSC1
[MCU2_1] 12.147560 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_MSC2
[MCU2_1] 12.147843 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_VISS1
[MCU2_1] 12.148096 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VDEC1
[MCU2_1] 12.148420 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VDEC2
[MCU2_1] 12.148691 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VENC1
[MCU2_1] 12.148957 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VENC2
[MCU2_1] 12.149431 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_CE_VISS
[MCU2_1] 12.152499 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:69] Added target VPAC_CE_RC
[MCU2_1] 12.152550 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[MCU2_1] 12.152577 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1] 12.199669 s: [TWEAK_STUB.INIT] Tweak is not compiled-in
[MCU2_1] 12.199723 s: [STORAGE_TRACE.INIT] Trace is not compiled-in
[MCU2_1] 12.200298 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1] 12.200343 s: UDMA Copy: Init ... !!!
[MCU2_1] 12.201693 s: UDMA Copy: Init ... Done !!!
[MCU2_1] 12.201742 s: APP: Init ... Done !!!
[MCU2_1] 12.201766 s: APP: Run ... !!!
[MCU2_1] 12.201785 s: IPC: Starting echo test ...
[MCU2_1] 12.204585 s: APP: Run ... Done !!!
[MCU2_1] 12.206139 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[.] C7X_1[.]
[MCU2_1] 12.206254 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[.]
[MCU2_1] 12.206332 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[.] C66X_1[P] C66X_2[P] C7X_1[.]
[MCU2_1] 12.206403 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[.]
[MCU2_1] 12.206476 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU2_1] 14.091608 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU3_0] 11.852294 s: CIO: Init ... Done !!!
[MCU3_0] 11.852368 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU3_0] 11.852410 s: APP: Init ... !!!
[MCU3_0] 11.852429 s: SCICLIENT: Init ... !!!
[MCU3_0] 11.852616 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[MCU3_0] 11.852655 s: SCICLIENT: DMSC FW revision 0x14
[MCU3_0] 11.852681 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_0] 11.852705 s: SCICLIENT: Init ... Done !!!
[MCU3_0] 11.852725 s: MEM: Init ... !!!
[MCU3_0] 11.852754 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3c00000 of size 2097152 bytes !!!
[MCU3_0] 11.852805 s: MEM: Init ... Done !!!
[MCU3_0] 11.852823 s: IPC: Init ... !!!
[MCU3_0] 11.852850 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_0] 11.859724 s: IPC: Init ... Done !!!
[MCU3_0] 11.859782 s: APP: Syncing with 7 CPUs ... !!!
[MCU3_0] 12.143918 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU3_0] 12.143951 s: REMOTE_SERVICE: Init ... !!!
[MCU3_0] 12.145478 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_0] 12.145539 s: APP: Init ... Done !!!
[MCU3_0] 12.145571 s: APP: Run ... !!!
[MCU3_0] 12.145595 s: IPC: Starting echo test ...
[MCU3_0] 12.148909 s: APP: Run ... Done !!!
[MCU3_0] 12.149888 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] C66X_1[x] C66X_2[x] C7X_1[P]
[MCU3_0] 12.150258 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[P]
[MCU3_0] 12.150749 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[P]
[MCU3_0] 12.150887 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU3_0] 12.205937 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU3_0] 14.091623 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[s] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU3_1] 11.915301 s: CIO: Init ... Done !!!
[MCU3_1] 11.915369 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU3_1] 11.915413 s: APP: Init ... !!!
[MCU3_1] 11.915431 s: SCICLIENT: Init ... !!!
[MCU3_1] 11.915611 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[MCU3_1] 11.915650 s: SCICLIENT: DMSC FW revision 0x14
[MCU3_1] 11.915677 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_1] 11.915703 s: SCICLIENT: Init ... Done !!!
[MCU3_1] 11.915724 s: MEM: Init ... !!!
[MCU3_1] 11.915752 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d3e00000 of size 2097152 bytes !!!
[MCU3_1] 11.915803 s: MEM: Init ... Done !!!
[MCU3_1] 11.915824 s: IPC: Init ... !!!
[MCU3_1] 11.915852 s: IPC: 8 CPUs participating in IPC !!!
[MCU3_1] 11.922757 s: IPC: Init ... Done !!!
[MCU3_1] 11.922816 s: APP: Syncing with 7 CPUs ... !!!
[MCU3_1] 12.143918 s: APP: Syncing with 7 CPUs ... Done !!!
[MCU3_1] 12.143952 s: REMOTE_SERVICE: Init ... !!!
[MCU3_1] 12.145472 s: REMOTE_SERVICE: Init ... Done !!!
[MCU3_1] 12.145532 s: APP: Init ... Done !!!
[MCU3_1] 12.145561 s: APP: Run ... !!!
[MCU3_1] 12.145583 s: IPC: Starting echo test ...
[MCU3_1] 12.148939 s: APP: Run ... Done !!!
[MCU3_1] 12.150025 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] C66X_1[x] C66X_2[x] C7X_1[P]
[MCU3_1] 12.150452 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[.] C66X_2[x] C7X_1[P]
[MCU3_1] 12.150756 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[.] C7X_1[P]
[MCU3_1] 12.150983 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU3_1] 12.205930 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU3_1] 14.091638 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
[C6x_1 ] 11.994158 s: CIO: Init ... Done !!!
[C6x_1 ] 11.994190 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
[C6x_1 ] 11.994204 s: APP: Init ... !!!
[C6x_1 ] 11.994211 s: SCICLIENT: Init ... !!!
[C6x_1 ] 11.994379 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[C6x_1 ] 11.994391 s: SCICLIENT: DMSC FW revision 0x14
[C6x_1 ] 11.994400 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ] 11.994409 s: SCICLIENT: Init ... Done !!!
[C6x_1 ] 11.994418 s: UDMA: Init ... !!!
[C6x_1 ] 11.995455 s: UDMA: Init ... Done !!!
[C6x_1 ] 11.995476 s: MEM: Init ... !!!
[C6x_1 ] 11.995488 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!!
[C6x_1 ] 11.995505 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ] 11.995520 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!!
[C6x_1 ] 11.995535 s: MEM: Init ... Done !!!
[C6x_1 ] 11.995543 s: IPC: Init ... !!!
[C6x_1 ] 11.995555 s: IPC: 8 CPUs participating in IPC !!!
[C6x_1 ] 11.999238 s: IPC: Init ... Done !!!
[C6x_1 ] 11.999266 s: APP: Syncing with 7 CPUs ... !!!
[C6x_1 ] 12.143916 s: APP: Syncing with 7 CPUs ... Done !!!
[C6x_1 ] 12.143927 s: REMOTE_SERVICE: Init ... !!!
[C6x_1 ] 12.144584 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_1 ] 12.144626 s: VX_ZONE_INIT:Enabled
[C6x_1 ] 12.144637 s: VX_ZONE_ERROR:Enabled
[C6x_1 ] 12.144647 s: VX_ZONE_WARNING:Enabled
[C6x_1 ] 12.145545 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[C6x_1 ] 12.145563 s: APP: OpenVX Target kernel init ... !!!
[C6x_1 ] 12.145854 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_1 ] 12.145875 s: UDMA Copy: Init ... !!!
[C6x_1 ] 12.147963 s: UDMA Copy: Init ... Done !!!
[C6x_1 ] 12.147982 s: APP: Init ... Done !!!
[C6x_1 ] 12.148210 s: APP: Run ... !!!
[C6x_1 ] 12.148221 s: IPC: Starting echo test ...
[C6x_1 ] 12.149849 s: APP: Run ... Done !!!
[C6x_1 ] 12.150304 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[.] C7X_1[P]
[C6x_1 ] 12.150530 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P]
[C6x_1 ] 12.150609 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[s] C66X_2[P] C7X_1[P]
[C6x_1 ] 12.150691 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P]
[C6x_1 ] 12.205801 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P]
[C6x_1 ] 14.091490 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[s] C66X_2[P] C7X_1[P]
[C6x_2 ] 12.064314 s: CIO: Init ... Done !!!
[C6x_2 ] 12.064347 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
[C6x_2 ] 12.064360 s: APP: Init ... !!!
[C6x_2 ] 12.064367 s: SCICLIENT: Init ... !!!
[C6x_2 ] 12.064535 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[C6x_2 ] 12.064547 s: SCICLIENT: DMSC FW revision 0x14
[C6x_2 ] 12.064556 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ] 12.064566 s: SCICLIENT: Init ... Done !!!
[C6x_2 ] 12.064575 s: UDMA: Init ... !!!
[C6x_2 ] 12.065617 s: UDMA: Init ... Done !!!
[C6x_2 ] 12.065638 s: MEM: Init ... !!!
[C6x_2 ] 12.065650 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!!
[C6x_2 ] 12.065668 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ] 12.065683 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!!
[C6x_2 ] 12.065699 s: MEM: Init ... Done !!!
[C6x_2 ] 12.065707 s: IPC: Init ... !!!
[C6x_2 ] 12.065719 s: IPC: 8 CPUs participating in IPC !!!
[C6x_2 ] 12.069430 s: IPC: Init ... Done !!!
[C6x_2 ] 12.069459 s: APP: Syncing with 7 CPUs ... !!!
[C6x_2 ] 12.143916 s: APP: Syncing with 7 CPUs ... Done !!!
[C6x_2 ] 12.143927 s: REMOTE_SERVICE: Init ... !!!
[C6x_2 ] 12.144587 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_2 ] 12.144630 s: VX_ZONE_INIT:Enabled
[C6x_2 ] 12.144641 s: VX_ZONE_ERROR:Enabled
[C6x_2 ] 12.144650 s: VX_ZONE_WARNING:Enabled
[C6x_2 ] 12.145546 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[C6x_2 ] 12.145564 s: APP: OpenVX Target kernel init ... !!!
[C6x_2 ] 12.145862 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_2 ] 12.145883 s: UDMA Copy: Init ... !!!
[C6x_2 ] 12.148072 s: UDMA Copy: Init ... Done !!!
[C6x_2 ] 12.148090 s: APP: Init ... Done !!!
[C6x_2 ] 12.148325 s: APP: Run ... !!!
[C6x_2 ] 12.148335 s: IPC: Starting echo test ...
[C6x_2 ] 12.150031 s: APP: Run ... Done !!!
[C6x_2 ] 12.150547 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[.]
[C6x_2 ] 12.150632 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] C66X_1[P] C66X_2[s] C7X_1[P]
[C6x_2 ] 12.150707 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
[C6x_2 ] 12.150888 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
[C6x_2 ] 12.205862 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
[C6x_2 ] 14.091533 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
[C7x_1 ] 12.141006 s: CIO: Init ... Done !!!
[C7x_1 ] 12.141028 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[C7x_1 ] 12.141043 s: APP: Init ... !!!
[C7x_1 ] 12.141051 s: SCICLIENT: Init ... !!!
[C7x_1 ] 12.141206 s: SCICLIENT: DMSC FW version [20.8.7-v2020.08d-1-gfcb08 (Terr]
[C7x_1 ] 12.141219 s: SCICLIENT: DMSC FW revision 0x14
[C7x_1 ] 12.141229 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ] 12.141239 s: SCICLIENT: Init ... Done !!!
[C7x_1 ] 12.141248 s: UDMA: Init ... !!!
[C7x_1 ] 12.141656 s: UDMA: Init ... Done !!!
[C7x_1 ] 12.141666 s: MEM: Init ... !!!
[C7x_1 ] 12.141677 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!!
[C7x_1 ] 12.141697 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
[C7x_1 ] 12.141716 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!!
[C7x_1 ] 12.141733 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ] 12.141750 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 234881024 bytes !!!
[C7x_1 ] 12.141768 s: MEM: Init ... Done !!!
[C7x_1 ] 12.141775 s: IPC: Init ... !!!
[C7x_1 ] 12.141785 s: IPC: 8 CPUs participating in IPC !!!
[C7x_1 ] 12.143890 s: IPC: Init ... Done !!!
[C7x_1 ] 12.143903 s: APP: Syncing with 7 CPUs ... !!!
[C7x_1 ] 12.143916 s: APP: Syncing with 7 CPUs ... Done !!!
[C7x_1 ] 12.143926 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ] 12.144179 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ] 12.144199 s: VX_ZONE_INIT:Enabled
[C7x_1 ] 12.144240 s: VX_ZONE_ERROR:Enabled
[C7x_1 ] 12.144251 s: VX_ZONE_WARNING:Enabled
[C7x_1 ] 12.144556 s: VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[C7x_1 ] 12.144570 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ] 12.144647 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ] 12.144661 s: APP: Init ... Done !!!
[C7x_1 ] 12.144670 s: APP: Run ... !!!
[C7x_1 ] 12.144679 s: IPC: Starting echo test ...
[C7x_1 ] 12.145349 s: APP: Run ... Done !!!
[C7x_1 ] 12.149731 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] C66X_1[x] C66X_2[x] C7X_1[s]
[C7x_1 ] 12.149821 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[x] C66X_2[x] C7X_1[s]
[C7x_1 ] 12.150289 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[.] C7X_1[s]
[C7x_1 ] 12.150433 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
[C7x_1 ] 12.205882 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
[C7x_1 ] 14.091561 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
Hi,
But you still have some components running on mcu2_0. Also where are you planning to run AEWB algo? Is it going to be on mcu2_0 or mcu2_1?
[MCU2_0] 14.085403 s: vissRemoteServer_Init ... Done !!!
[MCU2_0] 14.085453 s: IttRemoteServer_Init ... Done !!!
Regards,
Brijesh
We would like to move the AEWB algorithm to MCU2_1 in order to reduce the load.
Do we need to move the I2C and CSI_RX module as well? Please provide guide....
Please check tivxAddTargetKernelAewb API in imaging/kernels/arm/vx_aewb_target.c. I think AEWB is supported on both the cores mcu2_0 and mcu2_1.
Have you changed the target for AEWB node to mcu2_1 in your sample application by calling vxSetNodeTarget?
Most likely no, CSI_RX shouldn't require change.
Regards,
Brijesh
The function you mentioned is called from appRegisterOpenVXTargetKernels in App_init
and preprocessed with #define ENABLE_VHWA_VPAC, so it is confirmed that it is called in MCU2_1 as modified.
Currently, the sample application is stuck at vxVerifyGraph.
But what about Imaging nodes? Are they also running on mcu2_1? Also did you change target for the imaging node to be mcu2_1? If not, please change it in the your example and see if verify graph works?
