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TMDX654GPEVM: TMDX654XXXEVM PRU Access

MJ60
Prodigy 60 points

Part Number: TMDX654GPEVM

I have looked at the users guides for the TMDX654GPEVM & TMDX654IDKEVM. It is not clear if the boards provide external access to all three PRUs. The application connector shows GPIO pins connected to PRU0 and PRU1. I need to access all three for external connections to a a set of ADC chips. A dual core PRU is required to acquire and move data to main memory for each chip, as well as an additional PRU core to control the 3 wire SPI interface to the chips. I have implemented a single channel system on a Beagle Bone AI AM5729 and need to scale this up for the AM65xx.

Bottom Line;  Does the TMDX654 GP or IDK allow direct access to all three PRUs via pinmux config or other means for external input?

  • 0
    TI__Guru**** 192189 points

    Hello Michael Josh1,

    Thank you for the query.

    Have you looked at the below connector. 

    Looks like the available PRU signals for external connection are available on this connector.

    APPLICATION CONNECTOR

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 192189 points

    Hello Michael Josh1,

    I checked internally and the PRU signals have been terminated only to the APPLICATION CONNECTOR.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 60 points
    Sreenivasa,
    Thank you for the prompt reply.
    Yes I have examined the application connector description table in the user manuals for both the TMDX654
    IDK and GP boards.
    The tables list;
    PRG0_PRU0GPOx
    PRG0_PRU1GPOx
    PRG1_PRU0GPOx
    PRG1_PRU1GPOx
    This leads me to believe access is only to two of the three PRU cores. Possibly I have misunderstood the nomenclature.
    My original question still remains.
    Is there access to all three PRU processors from any connector on the board or via pinmux configuration?
    My application will require two dedicated dual core PRU processors for data acquisition and access to a third core for handling 3 wire SPI via bit banging. Unless I have also missed it it does not appear that 3 wire SPI ( bidirectional data line) is handled by any of the SPI interfaces on the board which would be another option.
  • +1 in reply to MJ60
    TI__Guru**** 192189 points

    Hello Michael Josh1,

    Thank you for the reply.

    The other PRU connects to the ethernet and i believe that is not being brought out on the connectors.

    Regards,

    Sreenivasa

  • 0 in reply to MJ60
    TI__Mastermind 47901 points
    MJ60 said:
    My application will require two dedicated dual core PRU processors for data acquisition and access to a third core for handling 3 wire SPI via bit banging. Unless I have also missed it it does not appear that 3 wire SPI ( bidirectional data line) is handled by any of the SPI interfaces on the board which would be another option.

    PRGx stands for one PRU-ICSSG instance, which has 6 PRU cores running at 250MHz max clock. Only PRU0 and PRU1 out of these 6 cores has IO access for output (GPO), input is visible from all 6 PRUs via R31 register.  Inter ICSSG latency is high, so it might be better to architect using one PRU-ICSSG if use case allows the same.

  • 0 in reply to PratheeshGangadhar
    TI__Guru**** 192189 points

    Hello Michael Josh1,

    Do you have an application block diagram including the data transfer rate, interface and the need for multiple PRU modules to be connected together? 

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 60 points

    Sreenvasa,

    I was trying to adapt an existing am5729 PRU project into a new board with a mandate of zero or minimal code changes. The existing project uses 1 PRU core to control the 3 wire SPI interface to an ADC chip. The data capture @ 32msps of 4 bit ADC is on the second PRU which pushes the data via XOUT/XIN to the other core which transfers the data to main memory. I believe I can accomplish the goal of reading two chips simultaneously by synchronizing the ADC chips sample clock. 'IF' that is doable then I can just have the PRU read 8 bits instead of four. The processing power of the Dual core A15 will be the limiting factor. I am also looking at running a baremetal app on the 5729 C66 core to offload the processing from the A15s. I have been using the BeagleBone AI as my proto board, but as you know there is limited TI support for that product. Ideally we can port the dual receiver to the 644x family and make minimal changes to the primary code.

  • 0 in reply to MJ60
    TI__Guru**** 192189 points

    Hello Michael Josh1,

    Thank you for the inputs on the use case. Appreciated. 

    Regards,

    Sreenivasa