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AM6411: Processor Peripherals: GPMC 32-bit A/D non-multiplexed interface

Franz Wudy
Prodigy 20 points
Part Number: AM6411
Other Parts Discussed in Thread: SYSCONFIG

Hello everybody,

we would like to evaluate the option of using the GPMC in 32-bit wide A/D non-multiplexed mode.


Document SPRUIM2E (9/2022, page 7417)
....
• External ... 32-bit pseudo-SRAM (pSRAM) device
....
seems to indicate that this is an option.

Table 12-3453, contains the pin-outs for
...
 - non-multiplexed Address Data 16-Bit Device
 - non-multiplexed Address Data 8-Bit Device
...
but not for non-multiplexed Address Data 32-bit Device.

Is it save to assume that in a 32-bit configuration GPMC0_AD[31]  .. GPMC0_AD[16] would act as data bits 31..16?
If so is it possible to add that to the manual?
If this mode will not work please -please correct me and also remove confusing hints from the tech specs.

Thanks for your help -

FW

  • 0
    TI__Guru**** 193249 points

    Hello FW,

    Thank you for the inputs.

    Franz Wudy said:
    we would like to evaluate the option of using the GPMC in 32-bit wide A/D non-multiplexed mode.

    Could you help us understand the use case.

     

    Franz Wudy said:
    External ... 32-bit pseudo-SRAM (pSRAM) device
    ....
    seems to indicate that this is an option.

    Will check internally and let them konw that this needs some additional dateils.

    I see the below modes described. And does not showcase the GPMC interface in 32-bit wide A/D non-multiplexed mode.

    12.3.3.2.1 GPMC Modes
    This section shows four GPMC0 external connection options:
    • Figure 12-1613 shows a connection between the GPMC0 and a 32-bit synchronous address/data-multiplexed
    external memory device.
    • Figure 12-1614 shows a connection between the GPMC0 and a 16-bit synchronous address/data-multiplexed
    (or AAD-multiplexed but this protocol uses fewer address pins) external memory device.
    • Figure 12-1615 shows a connection between the GPMC0 and a 16-bit synchronous non-multiplexed external
    memory device.
    • Figure 12-1616 shows a connection between the GPMC0 and an 8-bit synchronous non-multiplexed external
    memory device.
    • Figure 12-1617 shows a connection between the GPMC0 and an 8-bit NAND device. 

    I see that the 32-bit interface pins are connected on the device bit not sure on the constraints.

    6.3.11 GPMC
    6.3.11.1 MAIN Domain

    Have you tried the sysconfig to see if you have the 32-bit support.

    I will request the GPMC expert to review the inputs and the TRM sections to make any possible improvements.

    Regards,

    Sreenivasa

     

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru* 87040 points

    32-bit data using A/D non-muxed configuration is possible with AM64x.  Table 6-38 in the datasheet shows the pins that are used for GPMC0_A0-22 (for address) and GPMC0_AD0-31 (for data).  It's not a widely used configuration because of the amount of pins consumed, so that is partially the reason why it is not displayed in the TRM.  The pinmux tool https://dev.ti.com/sysconfig/#/config/?args=--device%20AM64x_beta%20--part%20Default%20--package%20ALV%20--theme%20light also supports this configuration

    Regards,

    james

  • 0 in reply to JJD
    Prodigy 20 points

    Hi James, thanks for your reply.

    This was helpful.

    Yet - the pinmux tool supports only 8- and 16-bit modes.

    Use-case: low-latency interconnect to a FPGA.

    Thanks -

    FW

  • 0 in reply to Franz Wudy
    TI__Guru* 87040 points

    Franz, yes i have submitted this bug against the pinmux tool.  If you choose "all pins of interface" for your use case, i believe this would be equivalent to the non-muxed 32bit data mode

    Regards,

    James