TMS320C6000 DSP (CPU) and DMA

All of the configuration writes to peripherals such as the DMA are memory mapped to the CPU, where the CPU will be performing loads and stores to memory addresses.
These accesses will ultimately get handled by a configuration bus.  A good illustration of this is represented in the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) on page 18 in Figure 1-1.
In this illustration, memory accesses to the device registers go through the L1D (Layer 1 Data) cache and will be picked up by the IDMA module which then sends these to the EMC (Extended Memory Controller).  The EMC then sends these accesses to the CFG (Configuration bus) to go to the device registers, which the EDMA3 would reside.

I'm sorry!
I didn't understand what you're asking. The device is TMS320C6202 DMA and CPU. Could you answer the question based in this member of the family TMS320C6000?
Realy sorry,
Thanks

Camila Nunes said:

The device is TMS320C6202 DMA and CPU.

First, I would suggest bookmarking, or at least reference the C6202B Product Folder, as the documents I reference below are pulled from there.

There is a good application note discussing the DMA and providing some examples in SPRA529.

In order to understand the C6202B architecture, I would suggest referencing the TMS320C620x/C670x DSP Program & Data Memory Controller/DMA Controller Ref.Guide.

On the C620x architecture, the DMA register set is accessed by the Peripheral Configuration bus through the Peripheral Bus Controller.  The Peripheral Bus Controller arbitrates accesses between the CPU Data Memory Controller (DMEMC) and the DMA.

Thanks for the answer and patience,

\o/