Hello,
I have tried the a pcie ethernet (rlt8111b) card on the ti8168 evm, and it doesn't work.
Lspci doesn't get anything.
Have somebody tried this card on the ti8168 evm?
Best regards
Andras
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Hello,
I have tried the a pcie ethernet (rlt8111b) card on the ti8168 evm, and it doesn't work.
Lspci doesn't get anything.
Have somebody tried this card on the ti8168 evm?
Best regards
Andras
Andras,
Can you provide the dump of PCIe register @ 0x51001728? I want to check the LTSSM status.
You can use devmem2 utility to read this register from shell prompt.
Thanks.
Hemant
Hemant,
I dumped the register. The value always changed.
0x0C004A07
0x0C002C06
0x0C003506
0x04009106
0x0C00F747
0x0C000007
0x0C00BC47
I tried other ethernet cards (rlt8168b, marvel 88e8053). It's happened same.
I tried a pcie usb card, and this works.
Thanks.
Andras
Andras,
Looks like you are using x1 card but the link negotiation is still remaining in link width negotiation.
Can you try applying following patch to the kernel (PCIe RC driver) - this patch forces x1 link? Note that depending upon the kernel version you are using the following patch may not apply as is and might require manual editing bu the important point is do use the workaround in the below patch just after "clk_enable()" call and before initiating link training.
Possible workaround for x1 link in case negotiation is stuck in link width configuration (please note that this is not verified - I just want to see if the LTSSM still remains in link-width negotiation or reaches link established state (last 5 bits in 0x51001728 become 0x11 on success):
--------------------------------------------------------------------------------------------------------------------------
diff --git a/arch/arm/mach-omap2/pcie-ti816x.c b/arch/arm/mach-omap2/pcie-ti816x.c
index 6a085b9..f3569da 100644
--- a/arch/arm/mach-omap2/pcie-ti816x.c
+++ b/arch/arm/mach-omap2/pcie-ti816x.c
@@ -660,6 +660,40 @@ static int ti816x_pcie_setup(int nr, struct pci_sys_data *sys)
goto err_clken;
/*
+ * WA: for x1 cards getting stuck in Configuration.Linkwidth.Start
+ */
+
+#define LINK_STAT_CTRL 0x80
+#define LINK_DISABLE_MASK (1 << 4)
+#define LINK_DISABLE_VAL (1 << 4)
+#define LINK_CAP 0x7C
+#define MAX_LINK_WIDTH_MASK (0x3F << 4)
+#define MAX_LINK_WIDTH_1X (1 << 4)
+#define MAX_LINK_SPEED_MASK (0xF)
+#define MAX_LINK_SPEED_GEN1 (1)
+
+ /*Disable Link */
+ __raw_writel(LINK_DISABLE_VAL | __raw_readl(reg_virt +
+ SPACE0_LOCAL_CFG_OFFSET + LINK_STAT_CTRL),
+ reg_virt + SPACE0_LOCAL_CFG_OFFSET + LINK_STAT_CTRL);
+
+ /* Set max width = x1, GEN1 */
+ __raw_writel(MAX_LINK_WIDTH_1X | MAX_LINK_SPEED_GEN1 |
+ (~(MAX_LINK_WIDTH_MASK | MAX_LINK_SPEED_MASK) &
+ __raw_readl(reg_virt + SPACE0_LOCAL_CFG_OFFSET +
+ LINK_CAP)),
+ reg_virt + SPACE0_LOCAL_CFG_OFFSET + LINK_CAP);
+
+ /* Enable link */
+ __raw_writel(~LINK_DISABLE_MASK & __raw_readl(reg_virt +
+ SPACE0_LOCAL_CFG_OFFSET + LINK_STAT_CTRL),
+ reg_virt + SPACE0_LOCAL_CFG_OFFSET + LINK_STAT_CTRL);
+
+ /*
+ * WA end
+ */
+
+ /*
* Initiate Link Training. We will delay for L0 as specified by
* standard, but will still proceed and return success irrespective of
* L0 status as this will be handled by explicit L0 state checks during
--------------------------------------------------------------------------------------------------------------------------------
Thanks.
Hemant
Andras,
Were you able to detect any of the cards with patch I sent in earlier post?
Thanks.
Hemant