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TDA4VM: A72 Warm Reset for BIST

David Dirks
Prodigy 100 points

Part Number: TDA4VM

Hello,

I am trying to figure out the proper registers needed to warm reset the A72 cores after a PBIST run on the A72 PBIST (and others requiring core resets).

My first issue is trying to change the state of the PD_A72_0, PD_A72_1, PD_A72_CLUSTER_0 from PD_ON, Enabled states to PD_OFF (Power States) SyncRst, SwRstDisabled, or Disabled (Module state) states. Following Concurrent Power Domain/Module State Transitions steps the GOSTAT never self clears when trying to turn off the cores. What am I missing here on the power down steps?

I also tried going through Sciclient_pmSetModuleRst API and following what was done but testing out different reset combinations with the PSC power domain and module states didn't result with the A72 working again without a complete POR.

Thanks,

David

  • 0
    TI__Guru 64895 points

    Hi David  

    You can refer to the example present in the pdk.

    You can find the referance code in 

    ti-processor-sdk-rtos-j721e-evm-08_04_00_06/sdl/test/pbist/pbist_ip/pbist_test_func.c

    You can find the steps to do the warm reset of  Main/Mcu R5 ,A72  C7x etc.

    To Download pdk 

    dr-download.ti.com/.../ti-processor-sdk-rtos-j721e-evm-08_05_00_11.tar.gz

    Regards
    Diwakar

  • 0 in reply to Diwakar Dhyani
    Prodigy 100 points

    Thanks for the response Diwakar.

    I have tried the steps from the PBIST_runTest function.

    My first question is around the PD_A72_0, PD_A72_1, PD_A72_CLUSTER_0 off and disable operations why the GOSTAT bit never clears when transitioning from an PSC on/ LPSC enabled state to anything else whether that is changing to PSC off, LPSC disabled, or both at the same time?

    The second question is around some of the functions not implemented yet:

    customPowerDownSequence

    customPrepareForPowerUpSequence

    Sciclient_procBootReleaseProcessor

    Sciclient_procBootReleaseProcessor

    We are not using the sciclient/server code combination which may be where my issue is with the complete warm reset as indicated by the example code.

    I don't see where the TISCI_MSG_PROC_REQUEST or TISCI_MSG_PROC_SET_CONTROL messages are handled by the sciserver?

    Any help would be appreciated.

  • 0 in reply to David Dirks
    TI__Guru 64895 points

    Hi David,

    Can you help me with the more information

    1.What is your boot flow.

    David Dirks said:

    We are not using the sciclient/server code combination which may be where my issue is with the complete warm reset as indicated by the example code.

    2.What combination you are using then .Do you mean to say you are not using  TISCI API ?

    3.Which sdk you are using?

    Regards
    Diwakar

  • 0 in reply to Diwakar Dhyani
    Prodigy 100 points

    Diwaker,

    1. Here is our boot process:

    1. Unlock MMR
    2. Set up pinmux
    3. Configure GPIO
    4. Start clocks
    5. Start uart
    6. Turn on A72 cluster 0
    7. Load Garmin secure OS to M4
      1. Wait for firewalls to be unlocked
    8. Turn on timers
    9. Powerup SPI for eMMC
    10. Disable l3 cache
    11. Power on EMIF PSC CFG 0/1 and Data 0/1 PSC/LPSC domains
    12. Turn on LBIST/PBIST PSC/LPSC domains and start non reset PBISTs
    13. Enable EMMC
    14. Clear DDR memory
    15. Init ECC on DDR
    16. Load kernel
    17. Set A72 to infinite loop
    18. Set reset vector for CPU to DDR base
    19. Set CPU to start in 64 bit ARM mode
    20. Power on A72_0, A72_1, and A72 PBIST PSC/LPSC power domains
    21. Start A72 and other PBIST/LBISTs that require core resetting – not working
    22. Check PBIST/LBIST status of tests run
    23. A72 boots properly, runs other boot up code from A72.

    2. We did not implement the TISCI API. We do not have any sci server running.

    3. Primarily using ti-processor-sdk-rtos-j721s2-evm-08_04_00_02 right now.


    Thanks!

    David

  • 0 in reply to David Dirks
    TI__Guru 64895 points

    Hi David 

    when you say 

    David Dirks said:
    • Power on A72_0, A72_1, and A72 PBIST PSC/LPSC power domains

    Are you saying you are triggering the PBIST for A72 from the A72 itself ?

    As PBIST is destructive in nature you should not do so in BIST example provided in the pdk we use MCU1_0 to trigger the bist for the other cores(main R5 , A72,C7X).

    Regards
    Diwakar

  • 0 in reply to Diwakar Dhyani
    Prodigy 100 points

    Diwakar

    All of the steps above are located on the R5 other than step 23. So the BISTs are all running from the R5.

    Thanks,
    David

  • 0 in reply to David Dirks
    TI__Guru 64895 points

    Hi David,

    Can you contact local FAE for this , to follow the proper channel for this issue.

    Regards
    Diwakar 

  • 0 in reply to Diwakar Dhyani
    Prodigy 100 points

    I contacted our FAE for this. Thanks Diwakar. I'll try to report back any solution we find.