Other Parts Discussed in Thread: DRA829, TDA4VM
(This is a re-post of the original thread.)
Hi experts,
Regarding the MSMC "shared coherent SRAM/cache", does it mean that when one core (e.g. C66x core 1) tries to read the L1 cache, if the data has been changed by another core (e.g. C66x core 0), the change will be reflected?
Also, where exactly does MSMC maintain coherence?
We looked at the J721E DRA829/TDA4VM TRM (spruil1c) and found the following description of the MSMC: "Shared coherent SRAM/cache".
[8.1.1 MSMC Overview] Page.826
MSMC supports the following features:
• 8MB (4 banks x 2MB) SRAM with ECC:
– Shared coherent level 2/level 3 memory-mapped SRAM
– Shared coherent level 3 cache
My customer has created a program using "PROCESSOR-SDK-RTOS" to check for "shared coherent".
1. read the top area of MSMC on core 0 of c66x -> write increment data to the top area repeatedly.
2. repeated reads of the top area of MSMC on core 1 of c66x.
We thought that the increment data written in step 1 would be incremented and read in step 2 because of the shared coherent cache. However, the data written in 1. was reflected only in the L1 cache, and there was no change in the L1 cache read in 2.
We would appreciate it if you could point out any errors in our understanding or checking methods.
Best regards,
O.H
