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AM625: DDR4 configuration & timing

Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG

Hello,

We have used TI EVK DDR4 part "MT40A1G16KD-062E IT:E" with AM625 CPU in one of our design. We do have few queries and need help on them.

1) Can we use TI EVK DDR4 sysconfig and timing parameters in our software because we have used same DDR4 part ?

2)  As we do not have followed exactly same TI EVK DDR4 layout (Lenth/Width/Spacing) in our design so in this case does skew compensation for the signals needed or not ? if needed then how we can do it because in DDR sys config tool we do not see any parameters related to skew compensation ?

Thanks,

Brijesh K

  • Brijesh, yes if you used the same device as on the EVM, you can use the same configuration file that comes with the SDK.  The only changes that you would possibly need to make is with the termination and drive strength values for both the memory and controller.  This will depend on your board layout, fab materials, and routing.  Ideal values would have come from board level signal integrity simulations.  

    The sysconfig tool will provide default skew compensation that is used by the controller/PHY during training.  During DDR initialization and training, these will be optimized by the training sequence of the PHY.  There aren't any parameters that you have to set in the sysconfig tool

    Regards,

    James

      

  • Hello JJD,

    sorry for late reply.

    Thank you so much for the valuable response.

    I do have one more question and need help on this as well please

    Is it possible to route the Linux/u-boot console logs on WKUP_UART0_TXD (C5) & WKUP_UART0_RXD (B4) instead of Main UART0 (D14 & E14) by doing any SW modifications?

    Thanks,

    Brijesh K

  • i will have to pass this on to our sw team

    James

  • Hi Brijesh,

    Yes, it is possible to modify U-Boot and kernel to use a different UART as the console, but please beware that the WKUP_UART0 isused by DM firmware as the debug console, so if you never needed to turn on DM firmware debug, its output would interfere with the Linux console output.

  • Hi Bin, 

    Actually not aware so asking. 

    As you said that " Yes, it is possible to modify U-Boot and kernel to use a different UART as the console, but please beware that the WKUP_UART0 isused by DM firmware as the debug console, so if you never needed to turn on DM firmware debug, its output would interfere with the Linux console output."

    In which case we may need to use DM firmware debug? 

    Is it not possible to use Linux console debug for all type of the interfaces usage? 

    Thanks, 

    Brijesh K

  • Hi Bin, 

    Actually not aware so asking. 

    As you said that " Yes, it is possible to modify U-Boot and kernel to use a different UART as the console, but please beware that the WKUP_UART0 isused by DM firmware as the debug console, so if you never needed to turn on DM firmware debug, its output would interfere with the Linux console output."

    In which case we may need to use DM firmware debug? 

    Is it not possible to use Linux console debug for all type of the interfaces usage? 

    Thanks, 

    Brijesh K

  • Hi Brijesh,

    In which case we may need to use DM firmware debug? 

    When any kernel code which fails to communicate with DM firmware, you would need to turn on DM firmware log to help the debugging.

    Is it not possible to use Linux console debug for all type of the interfaces usage? 

    I guess it is possible, but when all module logs (from DM firmware and Linux) are mixed into a single console, you would have a difficult time to identify which message is from where.

  • Hi Bin,

    Sorry for my late response and thank you so much for your valuable response.

    I do have one more question for the DDR testing.

    We have to perform DDR4 stress test to validate DDR4 performance at its full speed which is connected with AM6254 CPU .

    Can you please help us by suggesting how we can perform DDR4 stress test (test procedure) and what should be final outcome after completion of this test?

    thank you in advance.

    Regards,

    Brijesh K

  • Hi Brijesh,

    I am not sure what DDR stress test you want to perform, you need to define it and find the program to do so.

    The processor SDK provides a memory test tool - memtester, it can be used to check if DDR has read/write errors.

  • Hi Bin,

    Yes correct I was asking to check DDR read/write errors by doing stress test.

    Can you please suggest what process/steps need to perform for this test using memtester tool?

    Thanks,

    Brijesh K

  • root@am62xx-evm:~# memtester
    memtester version 4.3.0 (64-bit)
    Copyright (C) 2001-2012 Charles Cazabon.
    Licensed under the GNU General Public License version 2 (only).
    
    pagesize is 4096
    pagesizemask is 0xfffffffffffff000
    need memory argument, in MB
    
    Usage: memtester [-p physaddrbase [-d device]] <mem>[B|K|M|G] [loops]
    root@am62xx-evm:~#
    root@am62xx-evm:~# memtester 32M
    memtester version 4.3.0 (64-bit)
    Copyright (C) 2001-2012 Charles Cazabon.
    Licensed under the GNU General Public License version 2 (only).
    
    pagesize is 4096
    pagesizemask is 0xfffffffffffff000
    want 32MB (33554432 bytes)
    got  32MB (33554432 bytes), trying mlock ...locked.
    Loop 1:
      Stuck Address       : ok
      Random Value        : ok
      Compare XOR         : ok
      Compare SUB         : ok
      Compare MUL         : ok
      Compare DIV         : ok
      Compare OR          : ok
      Compare AND         : ok
      Sequential Increment: ok
      Solid Bits          : ok
      Block Sequential    : ok
      Checkerboard        : ok
      Bit Spread          : ok
      Bit Flip            : ok
      Walking Ones        : ok
      Walking Zeroes      : ok
    ...

  • Dear Bin,

    Thank you so much for this guidance, Will be in touch if any help needed further.

    Brijesh K