AM625: AM625X design issue

Hello Zhang Liang

Thank you for the query.

We would recommend to add queries specific to a subsystem or a peripheral in a single query with the title of the peripheral to reach wider audience.

Can you please edit the thread title to GPMC frequency.

I have the reply below for the GPMC frequency. and MMC

Zhang Liang said:

1. Please advise the max. operating rate for GPMC;

1× General-Purpose Memory Controller (GPMC)
up to 133 MHz

Reference - Datasheet 

Zhang Liang said:

Please avise the location for the PHY Caibration resistor in the design, we can't find it in the design;

As i understand the PHY calpad has not been pinned out. 

Reference - Datasheet 

Zhang Liang said:

3. Please advise if the SOC communicate to SOC with the RGMI;

4. Please advise how to use the LVDS to 2 channels, we consider to use the Lane1&2 to LVDS#1 and Lane3&4 to LVDS#2.

Please start a new thread for the RGMII interface.

For Q.4 please elaborate the query and the peripheral related to the query in a new thread.

Regards,

Sreenivasa

Hello Zhang Liang

I checked internally and have the updated information for the below. 

Kallikuppa Sreenivasa said:

Please avise the location for the PHY Caibration resistor in the design, we can't find it in the design;

This only applies to the MMC0 port of AM64x.  It does not apply to the MMC0 port of AM62x and the future AM62X devices.

The TRM is a generic diagram and refer datasheet for the availability of this pin.

Regards,

Sreenivasa

Hello Zhang Liang

Thank you for the note and appreciated.

Regards,

Sreenivasa