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66AK2G12: A15 GPMC accesses are interrupted too much by DSP write accesses

Koichiro Tashiro
Mastermind 22945 points
Part Number: 66AK2G12


Hi,

My customer reported below issue on 66AK2G12.

Scenario:
- Both Cortex-A15 and DSP are accessing to GPMC (same CS).
- A15 accesses are read, DSP accesses are write. A15 and DSP use single access.
- If both accesses occur simultaneously, A15 read accesses are interrupted by DSP write accesses.
One A15 access per 10 to 20 DSP accesses.


Waveform#1:


Waveform#2 (Zoom-up):


GPMC register configuration is attached.
GPMC_Regs.docx

Question:
I thought GPMC handles A15 and DSP accesses in a round-robin manner, but why DSP accesses are prioritized?
I checked TRM for arbitration configuration inside MSMC. It seems Bandwidth management (section 7.1.3.2.3)  only works for EMIF and SRAM.
System Master Interface is used for GPMC access, correct?

Thanks and regards,
Koichiro Tashiro

  • +1
    TI__Mastermind 27050 points

    What is the A15 MMU setting for the page where the reads are going? Is it strongly ordered? This means the A15 will send one read, and wait for it to complete. If another core like C66x is doing 10-20 posted writes (not blocking on each write) they can all get queued ahead of the one by one reads. Looking quickly through the memory access registers like MPAX and MAR on C66x I don't see similar control as with A15.

    My first suggesting would be a readback scenario to throttle the C66x writes, so each after each write read back the value, that should throttle the C66x writes. If this seems to help it will confirm it is the scenario above that is happening.

      Pekka

  • 0 in reply to Pekka Varis
    TI__Mastermind 22945 points

    Hi Pekka,

    Sorry for my late reply.

    Pekka Varis said:
    My first suggesting would be a readback scenario to throttle the C66x writes, so each after each write read back the value, that should throttle the C66x writes. If this seems to help it will confirm it is the scenario above that is happening.

    Customer tried above suggestion and it worked!

    Thanks and regards,
    Koichiro Tashiro