TMS320C6657: TMS320C6657 SPI

Hi Genady

Genady Chapovetsky said:

Required documentation to SPI peripherals on TMS320C6657: Interface registers definition.

In the product page, below, when we click "view-all" option, there are 80 technical documents. Those are the only documents for C6657.

https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf

 SPRUGP2A - This literature is the primary doc for SPI.

Genady Chapovetsky said:

The Literature Number: SPRUGP2A, March 2012 -- include lot of undefined.

To have a closer look on your query, would you please, point out the "undefined" ? 

Regards

Shankari G

Genady,

Good day!

 I could experiment on the SPI-NOR working code and verify about the SPIPC0 registers.

There is no need for SPIPC1 to SPIPC7 ------------> for C6657 unlike C674x/omapl13x.

---

To be more specific, if we set the value, "0x00000E01" to the SPIPC0 register, it is taken care internally and sets the value as "0x01010E01".

The user need not care for the bits 12 - 31 as they are reserved ones.

--

The optimal configuration would be settings just the "SPIPC0" -------------- ( No need of any other -- SPIPC1 to SPIPC7 ).

-----> The data sheet seems to be the right one with just the "SPIPC0" ----> https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf ---> page no:37

#define CSL_SPI_SPIPC0_SCS0FUN0_SHIFT ((uint32_t)0x00000000u)
#define CSL_SPI_SPIPC0_CLKFUN_SHIFT ((uint32_t)0x00000009u)
#define CSL_SPI_SPIPC0_SIMOFUN_SHIFT ((uint32_t)0x0000000Au)
#define CSL_SPI_SPIPC0_SOMIFUN_SHIFT ((uint32_t)0x0000000Bu)

#define CSL_SPI_SPIPC0_SCS0FUN0_SPI ((uint32_t)0x00000001u)
#define CSL_SPI_SPIPC0_CLKFUN_SPI ((uint32_t)0x00000001u)
#define CSL_SPI_SPIPC0_SIMOFUN_SPI ((uint32_t)0x00000001u)
#define CSL_SPI_SPIPC0_SOMIFUN_SPI ((uint32_t)0x00000001u)

SPI_SPIPC0 = (CSL_SPI_SPIPC0_SCS0FUN0_SPI << CSL_SPI_SPIPC0_SCS0FUN0_SHIFT) |
(CSL_SPI_SPIPC0_CLKFUN_SPI << CSL_SPI_SPIPC0_CLKFUN_SHIFT) |
(CSL_SPI_SPIPC0_SIMOFUN_SPI << CSL_SPI_SPIPC0_SIMOFUN_SHIFT) |
(CSL_SPI_SPIPC0_SOMIFUN_SPI << CSL_SPI_SPIPC0_SOMIFUN_SHIFT);

--

The following configuration is the complete working configuration of SPI interface.

/******************************************************************************
*
* Function: spi_claim
*
* Description: This function claims the SPI bus in the SPI controller
*
* Parameters: Uint32 cs - Chip Select number for the slave SPI device
* Uint32 freq - SPI clock frequency
*
* Return Value: error status
*
******************************************************************************/
SPI_STATUS
spi_claim
(
uint32_t cs,
uint32_t freq
)
{
uint32_t scalar;

PLIBSPILOCK()

/* Enable the SPI hardware */
SPI_SPIGCR0 = CSL_SPI_SPIGCR0_RESET_IN_RESET;
spi_delay (2000);
SPI_SPIGCR0 = CSL_SPI_SPIGCR0_RESET_OUT_OF_RESET;

/* Set master mode, powered up and not activated */
SPI_SPIGCR1 = (CSL_SPI_SPIGCR1_MASTER_MASTER << CSL_SPI_SPIGCR1_MASTER_SHIFT) |
(CSL_SPI_SPIGCR1_CLKMOD_INTERNAL << CSL_SPI_SPIGCR1_CLKMOD_SHIFT);


/* CS0, CS1, CLK, Slave in and Slave out are functional pins */
if (cs == 0) {

SPI_SPIPC0 = (CSL_SPI_SPIPC0_SCS0FUN0_SPI << CSL_SPI_SPIPC0_SCS0FUN0_SHIFT) |
(CSL_SPI_SPIPC0_CLKFUN_SPI << CSL_SPI_SPIPC0_CLKFUN_SHIFT) |
(CSL_SPI_SPIPC0_SIMOFUN_SPI << CSL_SPI_SPIPC0_SIMOFUN_SHIFT) |
(CSL_SPI_SPIPC0_SOMIFUN_SPI << CSL_SPI_SPIPC0_SOMIFUN_SHIFT);

} else if (cs == 1) {
SPI_SPIPC0 = ((CSL_SPI_SPIPC0_SCS0FUN1_SPI << CSL_SPI_SPIPC0_SCS0FUN1_SHIFT) |
(CSL_SPI_SPIPC0_CLKFUN_SPI << CSL_SPI_SPIPC0_CLKFUN_SHIFT) |
(CSL_SPI_SPIPC0_SIMOFUN_SPI << CSL_SPI_SPIPC0_SIMOFUN_SHIFT) |
(CSL_SPI_SPIPC0_SOMIFUN_SPI << CSL_SPI_SPIPC0_SOMIFUN_SHIFT)) & 0xFFFF;
}

/* setup format */
scalar = ((SPI_MODULE_CLK / freq) - 1 ) & 0xFF;

if ( cs == 0) {
SPI_SPIFMT0 = (8 << CSL_SPI_SPIFMT_CHARLEN_SHIFT) |
(scalar << CSL_SPI_SPIFMT_PRESCALE_SHIFT) |
(CSL_SPI_SPIFMT_PHASE_DELAY << CSL_SPI_SPIFMT_PHASE_SHIFT) |
(CSL_SPI_SPIFMT_POLARITY_LOW << CSL_SPI_SPIFMT_POLARITY_SHIFT) |
(CSL_SPI_SPIFMT_SHIFTDIR_MSB << CSL_SPI_SPIFMT_SHIFTDIR_SHIFT);
}else if ( cs == 1) {
SPI_SPIFMT0 = (16 << CSL_SPI_SPIFMT_CHARLEN_SHIFT) |
(scalar << CSL_SPI_SPIFMT_PRESCALE_SHIFT) |
(CSL_SPI_SPIFMT_PHASE_NO_DELAY << CSL_SPI_SPIFMT_PHASE_SHIFT) |
(CSL_SPI_SPIFMT_POLARITY_LOW << CSL_SPI_SPIFMT_POLARITY_SHIFT) |
(CSL_SPI_SPIFMT_SHIFTDIR_MSB << CSL_SPI_SPIFMT_SHIFTDIR_SHIFT);
}

/* hold cs active at end of transfer until explicitly de-asserted */
data1_reg_val = (CSL_SPI_SPIDAT1_CSHOLD_ENABLE << CSL_SPI_SPIDAT1_CSHOLD_SHIFT) |
(0x02 << CSL_SPI_SPIDAT1_CSNR_SHIFT);
if (cs == 0) {
SPI_SPIDAT1 = (CSL_SPI_SPIDAT1_CSHOLD_ENABLE << CSL_SPI_SPIDAT1_CSHOLD_SHIFT) |
(0x02 << CSL_SPI_SPIDAT1_CSNR_SHIFT);
}

/* including a minor delay. No science here. Should be good even with
* no delay
*/
if (cs == 0) {
SPI_SPIDELAY = (8 << CSL_SPI_SPIDELAY_C2TDELAY_SHIFT) |
(8 << CSL_SPI_SPIDELAY_T2CDELAY_SHIFT);
/* default chip select register */
SPI_SPIDEF = CSL_SPI_SPIDEF_RESETVAL;
} else if (cs == 1) {
SPI_SPIDELAY = (6 << CSL_SPI_SPIDELAY_C2TDELAY_SHIFT) |
(3 << CSL_SPI_SPIDELAY_T2CDELAY_SHIFT);
}

/* no interrupts */
SPI_SPIINT0 = CSL_SPI_SPIINT0_RESETVAL;
SPI_SPILVL = CSL_SPI_SPILVL_RESETVAL;

/* enable SPI */
SPI_SPIGCR1 |= ( CSL_SPI_SPIGCR1_ENABLE_ENABLE << CSL_SPI_SPIGCR1_ENABLE_SHIFT );

if (cs == 1) {
SPI_SPIDAT0 = 1 << 15;
spi_delay (10000);
/* Read SPIFLG, wait untill the RX full interrupt */
if ( (SPI_SPIFLG & (CSL_SPI_SPIFLG_RXINTFLG_FULL<<CSL_SPI_SPIFLG_RXINTFLG_SHIFT)) ) {
/* Read one byte data */
scalar = SPI_SPIBUF & 0xFF;
/* Clear the Data */
SPI_SPIBUF = 0;
}
else {
/* Read one byte data */
scalar = SPI_SPIBUF & 0xFF;
return SPI_EFAIL;
}
}
return SPI_EOK;
}

/******************************************************************************/

-------------------

To verify this, I did a small experiment. 

For example,

1. Set some dummy values like 0x00000001 to the SPIPC0

2. visualize the value of SPIPC0 register in the memory browser with address 0x20BF0014 ---> It will display the value as 0x00000001

3. Set the value as 0x00000E01 -----> the apt configuration to the SPIPC0 

4. visualize the value of SPIPC0 register in the memory browser with address 0x20BF0014 ---> It will display the value as 0x01010E01

 ---

I hope this helps!

Regards

Shankari G