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DRA821U: VDD_WAKE0 ramp timing requirement

ytakano
Genius 9095 points
Part Number: DRA821U
Other Parts Discussed in Thread: TLV62585

Hello,

Customer developed prototype board using DRA821U.
The power supply VDD_WAKE0 is driven by TLV62585 (DC/DC).
But it can not follow T2 timing requirement and will delay after T3 point.
In this case, will DRA821U work correct or not?


Regards,

  • +1
    TI__Expert 7065 points

    No, the customer's power sequence as shown will not meet recommended sequence requirements. Deviation from recommended sequence requirements can have negative impact to device reliability.

    The VDD_CPU & VDDA_0P8_xxx supplies should all ramp together with VDD_CORE. In addition, the VDD_CORE supply must ramp to operating voltage level before VDDAR_CORE, VDDAR_CPU & VDDS_DDR_xxx supplies.  Customer's power sequence must either remove the extra delay in ramping VDD_CORE or add same delay (+/- 300us) to the ramping of all concurrent (VDD_CPU & VDDA_0P8_xxx) & delayed (VDDAR_xxx, VDDS_DDR_xxx) supplies that has been introduced into VDD_CORE ramp. 

    Please note, a similar relationship exists between supplies during the power down sequences as well. Any delay in the ramp of VDD_CORE supply will need to be included in all concurrent & delayed supplies as well.

    Power sequences variations will need to be validated over full end product operational temperature range to ensure alignment to recommended power up & down sequences are maintained.