Hi
We are developing a new product based on the C6748 (d800k006, so silicon revision 2). So far, we used the Logic EVM to develop the software, but now it is time to port this to our custom board.
The custom board has a C6748 with an ISSI IS43DR16160A DDR2 chip. I'm trying to get this device to work at 102 MHz (a very low setting, hoping that that would be easier), but I have some troubles to get this device to work.
So far, I've used section 2.13 from SPRUGJ4B to understand the initialization sequence and the spreadsheet at http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x to calculate register values based on the ISSI chip. With those values and the initialization sequence from SPRUGJ4B, I've modified the C6748 gel file to try to bring the DDR2 chip to life, but so far no success.
While modifying the gel file, I noticed that the initialization routine for mDDR in the stock gel file skips step 3b (clear LOCK bit in VTPIO_CTL), step 6 (configure DDR_SLEW) and step 16 (configure PBBPR) from SPRUGJ4B. I've added them in my routine, and noticed that my custom board hangs when writing to DDR_SLEW. I've disabled the DDR_SLEW command, and then it completes the DDR initialization. I can then load and run a simple test program in IRAM. However, if that test program writes to the DDR memory (addresses 0xC000 0000 - 0xC000 0009), I get rubbish if I read it back later.
I have a few questions now:
1. SPRUGJ4B defines T_ODT as the minimum number of DDR_CLK cycles from ODT enable to write data driven. I cannot find this exact definition in the ISSI datasheet. The closest I could find was ODT turn-on delay, measured in units of tCK. (Actual value is 2 tCK.) I've used this value for T_ODT. Is that correct?
2. SPRUGJ4B defines EXT_STRBEN as a bit that selects external strobe gating. I am not very familiar with DDR (/DDR2) memory. What does this mean (both for hardware and software)? When is internal and when is external strobe gating required? Step 5a says to set EXT_STRBEN; is this different if one needs internal strobe gating? Or should you always use external strobe gating at this step?
3. Is it normal that my board hangs when writing to DDR_SLEW? Is setting DDR_SLEW necessary for DDR2? If so: why does the Logic C6748 gel file skip this step?
4. I think I have the correct settings for my DDR chip. Initialization routine seems to pass, but the device doesn't work. What is the best way to debug this?
5. Is there perhaps someone willing to check my DDR register settings with the ISSI datasheet (just to check that I didn't make any mistakes there)? I've added the my excel file with the timings as I understand them here: 
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For completeness:
My DDR init routine in my gel file is this:
DEVICE_DDR2ConfigISSI()
{
/*Enable the Clock to EMIF3A SDRAM*/
PSC1_LPSC_enable(PD0, LPSC_DDR);
/*If VTP calibration enabled , then skip the VTP calibration*/
if((VTPIO_CTL & 0x00000040))
{
// Begin VTP Calibration
VTPIO_CTL |= (0x00004000); // Set IOPWRDN bit to enable input buffer powerdown enable mode
VTPIO_CTL &= ~(0x00000040); // Clear POWERDN bit (enable VTP)
VTPIO_CTL &= ~(0x00000080); // Clear LOCK bit for static mode (not used for mDDR?)
// Pulse (low) CLRZ to initiate VTP IO Calibration
VTPIO_CTL |= (0x00002000); // Set CLRZ bit
VTPIO_CTL &= ~(0x00002000); // Clear CLRZ bit (CLRZ should be low for at least 2ns)
VTPIO_CTL |= 0x00002000; // Set CLZ bit
// Polling READY bit to see when VTP calibration is done
while(!((VTPIO_CTL & 0x00008000)>>15)) {}
VTPIO_CTL |= 0x00000080; // Set LOCK bit for static mode
VTPIO_CTL |= 0x00000100; // Set PWRSAVE bit to save power
// End VTP Calibration
}
// **********************************************************************************************
// Setting based on 512Mb mDDR MT46H32M16LFBF-6 on EVM
// Config DDR timings
DDRCTL = 0x00000085;
// Config DDR slew registers
//DDR_SLEW = 0x0;
EMIF3A_SDCR |= 0x00800000; // Set BOOTUNLOCK
EMIF3A_SDCR = 0x0017C822; // Clear BOOTUNLOCK and set SDCR settings
//EMIF3A_SDCR2 = 0x00000000; // for mDDR only
EMIF3A_SDTIMR1 = 0x0E492179;
EMIF3A_SDTIMR2 = 0x3D08C702;
EMIF3A_SDCR &= ~0x00008000; // Clear TIMUNLOCK
EMIF3A_SDRCR = 0xC000031B;
/*SyncReset the Clock to EMIF3A SDRAM*/
PSC1_LPSC_SyncReset(PD0, LPSC_DDR);
/*Enable the Clock to EMIF3A SDRAM*/
PSC1_LPSC_enable(PD0, LPSC_DDR);
EMIF3A_SDRCR &= ~0xC0000000; // disable self-refresh
EMIF3A_PBBPR = 0x20; // Set Peripheral Bus Burst Priority to moderately low valye (0x10 - 0x30)
}
This routine is called directly after Set_Core_100MHz() and Set_DDRPLL_102MHz(), just like the original Logic gel file did.
Any help is greatly appreciated.
Admar
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