I have a situation where the DSP (c6472) sends 2D frames out to the Back End (BE) DDR memory. I have setup the SRIO for peak data transfer rate of 2.5 Gbps (3.125 Gbps with 10/8). That leads to a data transfer BW of 300MBytes per second plus. The DDR in the BE could sometimes be in a state where it can only sustain a rate much lower than 300 MBytes per second because of other activities happening in the BE. Even in many other cases, it may be difficult for BE to sustain 300plus MBytes per second access rate (for the output from DSP).
We will be sending our output from DSP DDR.
My question is what happens in that case? Does the SRIO end point IP automatically take care of back pressure leading to overall rate dropping lower than peak? Or do we need to build a pacing mechanism using a GPIO?
In the case of former (that is automatic pacing) - does it lead to multiple retransmissions? is there any cost associated with that mechanism that we need to be aware of? Example does the automatic back pressure mechansim cause the switched central resource or any other resource within the DSP to slow down?
What would be a good document to study for such questions?
Somnath Banik