TMS320C6204: For power and clock supply sequence

O.H

Given that this is a 22+ year old part, I'll do my best to help.

O.H said:

Am I correct in understanding that there is no regulation on the sequence of supplying CVDD(PLLV), DVDD, and CLKIN?

Reviewing the datasheet, I did not find any dependencies. This paragraph suggests the same, at least for the supplies:

O.H said:

Is there any regulation on the rise time of the supply voltage of CVDD(PLLV) and DVDD?

The datasheet does not specify any requirements.

O.H said:

As background, my customer has changed some components in the power supply circuit (around CVDD(PLLV), DVDD) and is having a problem with PLL not working.(Nothing is output from CLKOUT1.)

Would be good to compare against the previous board.

Also, be sure to review the power supply design considerations listed in the datasheet, especially that the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up.  This suggests that the delay between CVDD and DVDD should be minimized. 

--Paul

Hello Paul,

PaulM said:

Given that this is a 22+ year old part, I'll do my best to help.

Sorry for late reply, and thank you so much for your support.

PaulM said:

Also, be sure to review the power supply design considerations listed in the datasheet, especially that the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up.  This suggests that the delay between CVDD and DVDD should be minimized. 

Could you please explain how the requirement to "the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up" might affect the problem of this PLL?
Even a possible view would be helpful. Since the datasheet does not specify the power supply sequence, they want to understand the validity of the measure.

Here is the progress.

• We are asking the customer to recheck the waveforms on the board before the change. (Because the measurement method was not correct).
• The point of difference in the temporary measurement is going to be the rise speed between 3.3V and 1.5V. (Before the change, they rise faster and almost at the same time.)
• It is working when the power from the board before the change is input directly to the DSP after the change.
• They are going to experiment with delaying the rise time of 1.5V enough to meet the requirement of "the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up".

Best regards,
O.H

I am afraid I no additional information to that detailed in the datasheet. 

If their new solution has less drive capability, perhaps that may be the issue?

—Paul

Hello Paul,

Thank you for support.

PaulM said:

I am afraid I no additional information to that detailed in the datasheet. 

This may be an unreasonable request, but would it be possible to share the power waveform of the C6701 EVM?

We have researched on the web and found that C6201EVM is recommended to evaluate C6205, and since there is a common manual for C6201EVM and C6701EVM, we think that C6701EVM may be the standard. But sorry, we do not own C6701EVM.
Currently, there is no provision in the datasheet, and as a customer, we do not have a reference waveform to show the adequacy of the countermeasure. The board before the modification (Pre-PCB) has a working PLL, but the power waveform has some suspicious points.
If there is no reference waveform, we believe that the customer has no choice but to fully evaluate the situation by themselves and determine the validity of the situation at their own discretion.

PaulM said:

If their new solution has less drive capability, perhaps that may be the issue?

Not sure if this answers your question. Additional information.

• The PLL did not work as a result of an experiment in which the timing of the rise of 1.5V was delayed sufficiently.
• The customer performed the following experiment to check on a board that was working properly after the change(OK-PCB), and the PLL worked.
  The regulator for 1.5V generation on OK-PCB was changed to one with fast rise time(from about  600us to 300us), and 3.3V and 1.5V were input from OK-PCB to the board with the problem (NG-PCB).

Best regards,
O.H

O.H said:

This may be an unreasonable request, but would it be possible to share the power waveform of the C6701 EVM?

I am not able to source this,

O.H said:

• The PLL did not work as a result of an experiment in which the timing of the rise of 1.5V was delayed sufficiently.
• The customer performed the following experiment to check on a board that was working properly after the change(OK-PCB), and the PLL worked.
  The regulator for 1.5V generation on OK-PCB was changed to one with fast rise time(from about  600us to 300us), and 3.3V and 1.5V were input from OK-PCB to the board with the problem (NG-PCB).

If I understand this, the change in in rise time resolved the issue?   

--Paul

Hello Paul,

Sorry for late reply.

PaulM said:

O.H said:

• The PLL did not work as a result of an experiment in which the timing of the rise of 1.5V was delayed sufficiently.
• The customer performed the following experiment to check on a board that was working properly after the change(OK-PCB), and the PLL worked.
  The regulator for 1.5V generation on OK-PCB was changed to one with fast rise time(from about  600us to 300us), and 3.3V and 1.5V were input from OK-PCB to the board with the problem (NG-PCB).

If I understand this, the change in in rise time resolved the issue? 

Additional experimentation shows that the PLL seems to work, especially if the rise time of the 1.5V line is accelerated.

There are 3 NG-PCBs and 500 OK-PCBs. The PLL works when the regulator on the 1.5V line of NG-PCB-1 is changed to a product with a faster rise time.

However, the OK-PCB uses a regulator with a slower rise time, but the PLL operates. Therefore, we have no information to prove that the rise time of the 1.5V line is a reasonable improvement.

Also, I have one question.

The behavior of CLKOUT2 is not consistent on boards with working PLLs, including OK-PCBs and modified NG-PCBs.
Is the following behavior normal for this device? Is there any possibility that this problem is caused by this issue?

For example.
After CLKOUT2 going High with the rising power supply, it oscillates without periodicity and suddenly stabilizes at 200MHz.
After CLKOUT2 goes High at the rising edge of the power supply, it remains High and suddenly stabilizes at 200MHz.
After CLKOUT2 going High for a moment at the rise of power supply, it keeps Low immediately and suddenly stabilizes at 200MHz.

Best regards,
O.H

O.H said:

For example.
After CLKOUT2 going High with the rising power supply, it oscillates without periodicity and suddenly stabilizes at 200MHz.
After CLKOUT2 goes High at the rising edge of the power supply, it remains High and suddenly stabilizes at 200MHz.
After CLKOUT2 going High for a moment at the rise of power supply, it keeps Low immediately and suddenly stabilizes at 200MHz.

Does CLKOUT1 exhibit the same behavior?  

When is reset released (in relation to CLKOUT2 becoming stable)? 

The datasheet shows that CLKOUT2 is undefined until 20ns (based on 200MHz CPU clock) after reset release. 

--Paul 

Hello Paul,

Thank you for your reply.

PaulM said:

Does CLKOUT1 exhibit the same behavior?  

When is reset released (in relation to CLKOUT2 becoming stable)? 

The datasheet shows that CLKOUT2 is undefined until 20ns (based on 200MHz CPU clock) after reset release. 

Yes. CLKOUT1 behaves in the same way. However, in the customer's waveform, CLKOUT1, and CLKOUT2 are definitely unstable for more than 20ns (about 1ms).
The reset pin state is always High when power is turned on. (It is pull-up by another 3.3V system.)

Could you provide a schematic(or the power supply IC used) of the TMS320C6201/6701EVM (TMS320C6xEVM) ?

The customer wants a regulator that works reliably and is not convinced by the idea of matching a regulator that has worked on past customer boards. I am hoping to find a regulator (or similar spec product) that has been tested to work like the EVM.

Best regards,
O.H

The best I could find was this: https://www.ti.com/lit/pdf/spru269?keyMatch=SPRU305